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Message
From: mdennis97@h...
Date: Fri, 16 May 2003 16:27:45 -0100
Subject: Re: [usb] Please help with a USB DPLL
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
To: usb@o...
Date: 15 May 2003 22:27:59 +0700
Subject: Re: [usb] Please help with a USB DPLL
>
>
> On Fri, 2003-05-16 at 00:50, mdennis97@h... wrote:
> > > Well, this phy was designed with full speed in mind only.
> > >
> > > Switching clocks is always a bad idea. Take a closer look
> > > how the DPLL works and how the actual 12Mhz clock is
> generated.
> > > If I remember correctly, everything runs at 48Mhz all the
> > > time, and I use clock enable to advance the rx and tx
> logic
> > > at a 1/4 speed 9e.g. 12 Mhz).
> >
> > Why not use a static 12Mhz clock for the transmit module?For
> many
> > applications, 12Mhz clock is always available.
>
> Sure, if all you need is Low Speed, that that would work.
One thing should be verified : if only Low Speed is required, the fs_ce
signal width must be keep 1 clk width(48 Mhz). And in this condition,
fs_ce works 1.5 Mhz. If the above two requirements are met, your
usb_tx_phy module might work except PRE pid which should be send in
Full Speed.
>
> If you need Full Speed as well, you need a 48 Mhz clock.
>
> Basically you need to do 4x oversampling to build a Digital PLL.
> (well, a decent one anyway !)
>
> > My guess would be that it
> > > would be a much cleaner solution to modify the DPLL to
> > > support LS speed mode.
> > >
> > > If you do make these modifications, please submit your
> > > work to OpenCores as well.
> > >
> > > rudi
>
>
> --
> rudi
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