|
Message
From: "henry_xb" <xxiaobin@2...>
Date: Fri, 16 May 2003 9:12:15 +0800
Subject: [usb] Re: usb-digest V1 #254
Hi friend:
I'd like to discuss the topic about DPLL. And there is anybody interest it?
Best Regard
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡henry_xb
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡xxiaobin@2...
¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2003-05-16
======= 2003-05-15 17:20:00 in Your email£º=======
> usb@o... usb-digest V1 #254
>
>
>----------------------------------------------------------------------
>From: mdennis97@h...
>Date: Thu, 15 May 2003 07:43:27 -0100
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>2003
>Received: (from majordomo@localhost)
> by www.opencores.org (8.12.8/8.12.8) id h4F8hVfj018318
> for usb-list; Thu, 15 May 2003 07:43:31 -0100
>X-Authentication-Warning: localhost.localdomain: majordomo set sender to owner-usb@o... using -f
>Received: (from oc@localhost)
> by www.opencores.org (8.12.8/8.12.8) id h4F8hRjI018291
> for usb@o...; Thu, 15 May 2003 07:43:27 -0100
>Date: Thu, 15 May 2003 07:43:27 -0100
>X-Virus: 6
>Message-Id: <200305150843.h4F8hRjI018291@w...>
>Subject: Re: [usb] Please help with a USB DPLL
>To: usb@o...
>From: mdennis97@h...
>Sender: owner-usb@o...
>Precedence: bulk
>Reply-To: usb@o...
>
>Thanks, Mr. rudi:
> The usb phy you have contributed uses 48mhz as its clock.Taking into
>account the host side applications, host controller may signal in low
>speed and full speed. In this condition, I don't know if a single phy can
>deal with those tasks. If it does, when working at low speed, can we
>connect the clk signal of the phy to a 6mhz clock which may be derived
>from the 48mhz?
> Furthermore, after having completed the low speed transaction, the
>phy clock should be switched back to 48mhz. Does this suppositon work?
>
>Regards
>
>Dennis
>
>----- Original Message -----
>From: Rudolf Usselmann <rudi@a... >
>To: usb@o...
>Date: 13 May 2003 13:01:41 +0700
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>>
>>
>> On Tue, 2003-05-13 at 15:19, mdennis97@h... wrote:
>> > hi, Mr. rudi:
>> >
>> > As far as I know, your dpll is based on full speed. If there
>> is a low
>> > speed device to be applied, how to modify this logic core?That
>> is, for
>> > the host controller, can we use your dpll for a reference?
>> > Maybe it's a difficult project.
>> >
>> > Regards
>> >
>> > Dennis
>>
>> Just modify it to generate 1.5 Mhz clock enables - use
>> every 8th one from 12 Mhz ...
>> Or modify the FSM accordingly ... should be trivial
>>
>>
>>
>> rudi
>> -------------------------------------------------------
>> www.asics.ws -- Solutions for your ASIC/FPGA needs ---
>> ---------------- FPGAs * Full Custom ICs * IP Cores ---
>> * * * FREE IP Cores --> http://www.asics.ws/ <-- * * *
>>
>
>
>----------------------------------------------------------------------
>From: Rudolf Usselmann <rudi@a...>
>Date: 15 May 2003 13:20:38 +0700
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>On Thu, 2003-05-15 at 15:43, mdennis97@h... wrote:
>> Thanks, Mr. rudi:
>> The usb phy you have contributed uses 48mhz as its clock.Taking into
>> account the host side applications, host controller may signal in low
>> speed and full speed. In this condition, I don't know if a single phy can
>> deal with those tasks. If it does, when working at low speed, can we
>> connect the clk signal of the phy to a 6mhz clock which may be derived
>> from the 48mhz?
>> Furthermore, after having completed the low speed transaction, the
>> phy clock should be switched back to 48mhz. Does this suppositon work?
>>
>> Regards
>>
>> Dennis
>
>Well, this phy was designed with full speed in mind only.
>
>Switching clocks is always a bad idea. Take a closer look
>how the DPLL works and how the actual 12Mhz clock is generated.
>If I remember correctly, everything runs at 48Mhz all the
>time, and I use clock enable to advance the rx and tx logic
>at a 1/4 speed 9e.g. 12 Mhz). My guess would be that it
>would be a much cleaner solution to modify the DPLL to
>support LS speed mode.
>
>If you do make these modifications, please submit your
>work to OpenCores as well.
>
>rudi
>-------------------------------------------------------
>www.asics.ws -- Solutions for your ASIC/FPGA needs ---
>---------------- FPGAs * Full Custom ICs * IP Cores ---
>* * * FREE IP Cores --> http://www.asics.ws/ <-- * * *
>
>
>
>
>
>----------------------------------------------------------------------
>From: mdennis97@h...
>Date: Thu, 15 May 2003 10:44:29 -0100
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>2003
>Received: (from majordomo@localhost)
> by www.opencores.org (8.12.8/8.12.8) id h4FBiXa6002912
> for usb-list; Thu, 15 May 2003 10:44:33 -0100
>X-Authentication-Warning: localhost.localdomain: majordomo set sender to owner-usb@o... using -f
>Received: (from oc@localhost)
> by www.opencores.org (8.12.8/8.12.8) id h4FBiTmH002867
> for usb@o...; Thu, 15 May 2003 10:44:29 -0100
>Date: Thu, 15 May 2003 10:44:29 -0100
>X-Virus: 6
>Message-Id: <200305151144.h4FBiTmH002867@w...>
>Subject: Re: [usb] Please help with a USB DPLL
>To: usb@o...
>From: mdennis97@h...
>Sender: owner-usb@o...
>Precedence: bulk
>Reply-To: usb@o...
>
>ok. I will try. And your advice will be the best help.
>
>----- Original Message -----
>From: Rudolf Usselmann <rudi@a... >
>To: usb@o...
>Date: 15 May 2003 13:20:38 +0700
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>>
>>
>> On Thu, 2003-05-15 at 15:43, mdennis97@h... wrote:
>> > Thanks, Mr. rudi:
>> > The usb phy you have contributed uses 48mhz as its
>> clock.Taking into
>> > account the host side applications, host controller may signal
>> in low
>> > speed and full speed. In this condition, I don't know if a
>> single phy can
>> > deal with those tasks. If it does, when working at low speed,
>> can we
>> > connect the clk signal of the phy to a 6mhz clock which may be
>> derived
>> > from the 48mhz?
>> > Furthermore, after having completed the low speed
>> transaction, the
>> > phy clock should be switched back to 48mhz. Does this
>> suppositon work?
>> >
>> > Regards
>> >
>> > Dennis
>>
>> Well, this phy was designed with full speed in mind only.
>>
>> Switching clocks is always a bad idea. Take a closer look
>> how the DPLL works and how the actual 12Mhz clock is generated.
>> If I remember correctly, everything runs at 48Mhz all the
>> time, and I use clock enable to advance the rx and tx logic
>> at a 1/4 speed 9e.g. 12 Mhz). My guess would be that it
>> would be a much cleaner solution to modify the DPLL to
>> support LS speed mode.
>>
>> If you do make these modifications, please submit your
>> work to OpenCores as well.
>>
>> rudi
>> -------------------------------------------------------
>> www.asics.ws -- Solutions for your ASIC/FPGA needs ---
>> ---------------- FPGAs * Full Custom ICs * IP Cores ---
>> * * * FREE IP Cores --> http://www.asics.ws/ <-- * * *
>>
>
>
>----------------------------------------------------------------------
>From: mdennis97@h...
>Date: Thu, 15 May 2003 16:50:01 -0100
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>2003
>Received: (from majordomo@localhost)
> by www.opencores.org (8.12.8/8.12.8) id h4FHo3dM029486
> for usb-list; Thu, 15 May 2003 16:50:03 -0100
>X-Authentication-Warning: localhost.localdomain: majordomo set sender to owner-usb@o... using -f
>Received: (from oc@localhost)
> by www.opencores.org (8.12.8/8.12.8) id h4FHo1se029440
> for usb@o...; Thu, 15 May 2003 16:50:01 -0100
>Date: Thu, 15 May 2003 16:50:01 -0100
>X-Virus: 6
>Message-Id: <200305151750.h4FHo1se029440@w...>
>Subject: Re: [usb] Please help with a USB DPLL
>To: usb@o...
>From: mdennis97@h...
>Sender: owner-usb@o...
>Precedence: bulk
>Reply-To: usb@o...
>
>----- Original Message -----
>From: Rudolf Usselmann <rudi@a... >
>To: usb@o...
>Date: 15 May 2003 13:20:38 +0700
>X-Virus: 6
>Subject: Re: [usb] Please help with a USB DPLL
>
>>
>>
>> On Thu, 2003-05-15 at 15:43, mdennis97@h... wrote:
>> > Thanks, Mr. rudi:
>> > The usb phy you have contributed uses 48mhz as its
>> clock.Taking into
>> > account the host side applications, host controller may signal
>> in low
>> > speed and full speed. In this condition, I don't know if a
>> single phy can
>> > deal with those tasks. If it does, when working at low speed,
>> can we
>> > connect the clk signal of the phy to a 6mhz clock which may be
>> derived
>> > from the 48mhz?
>> > Furthermore, after having completed the low speed
>> transaction, the
>> > phy clock should be switched back to 48mhz. Does this
>> suppositon work?
>> >
>> > Regards
>> >
>> > Dennis
>>
>> Well, this phy was designed with full speed in mind only.
>>
>> Switching clocks is always a bad idea. Take a closer look
>> how the DPLL works and how the actual 12Mhz clock is generated.
>> If I remember correctly, everything runs at 48Mhz all the
>> time, and I use clock enable to advance the rx and tx logic
>> at a 1/4 speed 9e.g. 12 Mhz).
>
>Why not use a static 12Mhz clock for the transmit module?For many
>applications, 12Mhz clock is always available.
>
>My guess would be that it
>> would be a much cleaner solution to modify the DPLL to
>> support LS speed mode.
>>
>> If you do make these modifications, please submit your
>> work to OpenCores as well.
>>
>> rudi
>> -------------------------------------------------------
>> www.asics.ws -- Solutions for your ASIC/FPGA needs ---
>> ---------------- FPGAs * Full Custom ICs * IP Cores ---
>> * * * FREE IP Cores --> http://www.asics.ws/ <-- * * *
>>
>
>
>----------------------------------------------------------------------
>End of usb-digest V1 #254
>-
>To unsubscribe from usb-digest mailing list please visit
http://www.opencores.org/mailinglists.shtml
= = = = = = = = = = = = = = = = = = = =
|
 |
Browse
