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Message
From: mdennis97@h...
Date: Thu, 15 May 2003 07:43:27 -0100
Subject: Re: [usb] Please help with a USB DPLL
Thanks, Mr. rudi:
The usb phy you have contributed uses 48mhz as its clock.Taking into
account the host side applications, host controller may signal in low
speed and full speed. In this condition, I don't know if a single phy can
deal with those tasks. If it does, when working at low speed, can we
connect the clk signal of the phy to a 6mhz clock which may be derived
from the 48mhz?
Furthermore, after having completed the low speed transaction, the
phy clock should be switched back to 48mhz. Does this suppositon work?
Regards
Dennis
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
To: usb@o...
Date: 13 May 2003 13:01:41 +0700
Subject: Re: [usb] Please help with a USB DPLL
>
>
> On Tue, 2003-05-13 at 15:19, mdennis97@h... wrote:
> > hi, Mr. rudi:
> >
> > As far as I know, your dpll is based on full speed. If there
> is a low
> > speed device to be applied, how to modify this logic core?That
> is, for
> > the host controller, can we use your dpll for a reference?
> > Maybe it's a difficult project.
> >
> > Regards
> >
> > Dennis
>
> Just modify it to generate 1.5 Mhz clock enables - use
> every 8th one from 12 Mhz ...
> Or modify the FSM accordingly ... should be trivial
>
>
>
> rudi
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