|
Message
From: Rudolf Usselmann <rudi@a...>
Date: 13 May 2003 13:01:41 +0700
Subject: Re: [usb] Please help with a USB DPLL
On Tue, 2003-05-13 at 15:19, mdennis97@h... wrote:
> hi, Mr. rudi:
>
> As far as I know, your dpll is based on full speed. If there is a low
> speed device to be applied, how to modify this logic core?That is, for
> the host controller, can we use your dpll for a reference?
> Maybe it's a difficult project.
>
> Regards
>
> Dennis
Just modify it to generate 1.5 Mhz clock enables - use
every 8th one from 12 Mhz ...
Or modify the FSM accordingly ... should be trivial
rudi
-------------------------------------------------------
www.asics.ws -- Solutions for your ASIC/FPGA needs ---
---------------- FPGAs * Full Custom ICs * IP Cores ---
* * * FREE IP Cores --> http://www.asics.ws/ <-- * * *
|
 |
Browse
