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Message
From: Rudolf Usselmann <rudi@a...>
Date: 13 May 2003 01:04:34 +0700
Subject: Re: [usb] Please help with a USB DPLL
'a' and 'b' are just two different sync stages the state
machine can be in. The resulting clock from either stage
is 12 Mhz. I personally find the example in siewp.pdf way
to over-engineered. I wrote a USB 1.1 PHY with a simple 4
stage state machine, and have tested it in hardware. It
appears to work just fine. I have never understood the extra
complexity in the siewp.pdf.
See OC for the PHY ...
Regards,
rudi
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