Hi,

 

Im trying to design a 'Digital Phase Locked Loop' for a USB signal in VHDL.  To do this im using the 'State Machine' from the document siewp.pdf (Designing a Robust Serial Interface Engine) found on the usb.org website.  I beleive the state machine is on page 3.  The problem im having is that the state machine refers to 'a' and 'b' as being synced on the rising and falling edges.  Do this mean that 'a' and 'b' are synced on the rising and falling edges of the 48MHz clock?

 

If this is the case then isn't the output from the DPLL 24MHz, rather than 12MHz?

 

Can anyone give a working description of the 'State Machine'?

 

If anyone can help with this then please do.

 

Thanks,