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Message
From: roger.garcia@l...
Date: Fri, 21 Mar 2003 21:02:50 -0100
Subject: RE: [usb] USB soft core (VHDL)
I too am looking for a VHDL core. However, what I plan on trying is to
import the verilog code into a synthesis tool, and export a VHDL netlist.
Most current synthesis tools will read VHDL and Verilog languages and
give you the capability to export a VHDL netlist. I plan on treating that
netlist as a black box module. The rest of my design is VHDL, but at the
top level, will instantiate the VHDL netlist IP core into my design.
Roger
----- Original Message -----
From: "Vikas T Rao " <vikasraot@m... >
To: <usb@o... >
Date: Tue, 04 Feb 2003 15:15:24 +0530
Subject: RE: [usb] USB soft core (VHDL)
>
>
> there are tools(Visual HDL) which convert from verilog to vhdl and
> vice-versa. probably u try that after u don't get any vhdl code in
> web.
>
> >>> vanbaarleb@t... 02/04/03 02:56PM >>>
> Thank you for your reply Vikas, but I'm afraid that's not quite
> helping
> me.
> I'm using some good design and simulation tools for VHDL (which I
> would
> like
> to keep using in the future) and it's working fine, but I find it
> weird
> that
> there isn't an USB open core in VHDL. John (Deepu C) mentioned it
> before
> that not everybody is into Verilog. ...so I keep continue
> searching.
>
> Bart
>
> -----Original Message-----
> From: Vikas T Rao [mailto:vikasraot@m... ]
> Sent: 04 February 2003 09:58
> To: usb@o...
> Subject: Re: [usb] USB soft core (VHDL)
>
>
> hi,
>
> probably only thing u can do is learn verilog. verilog is easy and
> will
> take only 10 days max to learn it.
>
> BEST OF LUCK.
>
> ...vikas.
>
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