LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Usb > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: tangyj@v...
    Date: Mon, 17 Mar 2003 08:46:52 -0100
    Subject: [usb] usb2.0 question
    Top

    I have some questions about usb2.0 PHY's digital parts:
    1. Because of bit-unstuff , a 60M clk may be have not enough bit to get
    (may be 7-bit),how can I organize the timing of 480M and 60M?
    2. when receiving,the 480M clk is synchronized to the data,the 60M clk 
    is also synchronized to the data?
    
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.