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From: Rudolf Usselmann <rudi@a...>
Date: 20 Feb 2003 16:33:22 +0700
Subject: Re: [usb] Re: usb-digest V1 #228

On Thu, 2003-02-20 at 13:44, henry_xb wrote:
> Hi usb-digest！
> 
> I have simulated the DPLL state machine ,but when the input frequency (12M)-0.4% ,the data registered by the extracted clock will error .And the total number of receive bits lest than 8192.  
> Can tell me why ,my friends?
> thanks  
> 			
> Best Regard
> 
> henry_xb
> 　　　　　　　　xxiaobin@2...
> 　　　　　　　　　　2003-02-20

Perhaps this is why the USB spec specifies an 0.25%
maximum clock error rate ?

Your 0.4% clock error rate violates USB specification.

See Chapter 7.1.11 in the USB 1.1 spec.


rudi
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Reference Author

[usb] Re: usb-digest V1 #228 Henry_xb