LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Usb > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: "Vikas T Rao " <vikasraot@m...>
    Date: Tue, 04 Feb 2003 15:15:24 +0530
    Subject: RE: [usb] USB soft core (VHDL)
    Top

    there are tools(Visual HDL) which convert from verilog to vhdl and
    vice-versa. probably u try that after u don't get any vhdl code in web.
    
    >>> vanbaarleb@t... 02/04/03 02:56PM >>>
    Thank you for your reply Vikas, but I'm afraid that's not quite helping
    me.
    I'm using some good design and simulation tools for VHDL (which I would
    like
    to keep using in the future) and it's working fine, but I find it weird
    that
    there isn't an USB open core in VHDL. John (Deepu C) mentioned it
    before
    that not everybody is into Verilog. ...so I keep continue searching.
    
    Bart 
    
    -----Original Message-----
    From: Vikas T Rao [mailto:vikasraot@m...] 
    Sent: 04 February 2003 09:58
    To: usb@o... 
    Subject: Re: [usb] USB soft core (VHDL)
    
    
    hi,
    
    probably only thing u can do is learn verilog. verilog is easy and
    will
    take only 10 days max to learn it.
    
    BEST OF LUCK.
    
    ...vikas.
    
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.