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Message
From: van Baarle Bart <vanbaarleb@t...>
Date: Tue, 4 Feb 2003 10:26:54 +0100
Subject: RE: [usb] USB soft core (VHDL)
Thank you for your reply Vikas, but I'm afraid that's not quite helping me.
I'm using some good design and simulation tools for VHDL (which I would like
to keep using in the future) and it's working fine, but I find it weird that
there isn't an USB open core in VHDL. John (Deepu C) mentioned it before
that not everybody is into Verilog. ...so I keep continue searching.
Bart
-----Original Message-----
From: Vikas T Rao [mailto:vikasraot@m...]
Sent: 04 February 2003 09:58
To: usb@o...
Subject: Re: [usb] USB soft core (VHDL)
hi,
probably only thing u can do is learn verilog. verilog is easy and will
take only 10 days max to learn it.
BEST OF LUCK.
...vikas.
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