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Message
From: "M Dennis" <mdennis97@h...>
Date: Wed, 04 Dec 2002 04:28:30 -1000
Subject: [usb] dout of usb 1.1 function core
hi,rudi
I am a little confused with your USB 1.1 Function IP Core.In usb1_core.v,
// In endpoints only
always @(posedge clk_i)
case(ep_sel) // synopsys full_case parallel_case
4'h0: tx_data_st <= #1 ep0_dout;
4'h1: tx_data_st <= #1 ep1_din; // why not ep1_dout?
4'h2: tx_data_st <= #1 ep2_din;
4'h3: tx_data_st <= #1 ep3_din;
4'h4: tx_data_st <= #1 ep4_din;
4'h5: tx_data_st <= #1 ep5_din;
4'h6: tx_data_st <= #1 ep6_din;
4'h7: tx_data_st <= #1 ep7_din;
endcase
epn_din is input wire,which should not connected to assigned to an output
port,isn't it?I think the data stream will flow from epn_dout to PL module
via tx_data_st.
Similar dout to the following code in the same file.
assign ep1_dout = rx_data_st;
assign ep2_dout = rx_data_st;
assign ep3_dout = rx_data_st;
assign ep4_dout = rx_data_st;
assign ep5_dout = rx_data_st;
assign ep6_dout = rx_data_st;
assign ep7_dout = rx_data_st;
Please clarify them.
Reagards
Dennis
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