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hi:
  i faced the same problem,when i wan to send some package
to test my core,how can i find good package,can you help me?
                  thanks

----- Original Message ----- 
From: Rudolf Usselmann <rudi@a... > 
To: usb@o...  
Date: Sun, 31 Mar 2002 13:22:35 +0700 
Subject: Re: [usb] some question about the code of the USB 
function 
core 

> 
> 
> On Saturday 30 March 2002 02:40 pm, you wrote: 
> > Hi,Rudi and all: 
> > 
> >    I have some questions about the USB function core. 
> > The first is that how can I re-simulate the core as I 
cannot 
> > find anything in the dictory of bench. I want to learn how 
> > to get a full simulation about the core. 
> 
> How about writing a test bench ??? 
> 
> I've been asking for someone to help to write a test bench, 
but 
> nobody wants to do it ... 
> 
> > The second is that I have seen some code in the module of 
the 
> core 
> > like that following : 
> > 
> > always @(posedge clk) 
> > 	clr_sof_time <= #1 frame_no_we; 
> >                     ~~~~~ that means to assign the value 
after 
> one unit 
> > time 
> > 
> > In my opinion, to add one unit time delay in the code is 
to 
> minimize 
> > the difference between the RTL simulation and the 
synthesized 
> gate-level 
> > simulation. But that code may not be supported by the 
> synthesis tools. 
> > Is that true ? How can I change the core into 
synthesisable ? 
> 
> No this does not bring rtl closer to gate level simulations. 
Timing 
> will always differ depending on your technology. The "#1" is 
really 
> absolutely meaningless. The only reason I like to add them 
is 
> because it makes debugging of rtl so much easier. 
> 
> This core is absolutely 100% synthesizable. Every synthesis 
tool 
> will ignore the "#1". 
> 
> rudi 
> 
> > Thanks for your answer. 
> > 
> > Best regards. 
> > 
> > 
> > Jiang daosan 
> > jiangdaosan@2...  
>