LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Usb > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: b_makkiabadi@y...
    Date: Wed, 22 May 2002 14:31:51 +0200
    Subject: Re: [usb] USB CORE IN VHDL
    Top

    
    
    ----- Original Message ----- 
    From: gr6@u...  
    To: usb@o...  
    Date: Tue, 01 May 2001 22:40:45 +0100 (BST) 
    Subject: [usb] USB CORE IN VHDL 
    
    > 
    > 
    > HELLO, 
    > I AM LOOKING FOR FREE USB (V:2.0) CORE WRITTEN IN VHDL. 
    > 
    > THANK YOU 
    >
    
    Hi dear unknown
    i am searching for free usb cores like you.
    but i didn't find a Synthetizeable usb core for my studental 
    project "transferring ecg signal from usb bus".
    do you have ver 1.0  usb Synthetizeable  core  ??
    if you have please help me for my project. 
    bahador makki biomedical eng. ms.student
    thanks ,
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.