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Message
From: Mark<mark@j...>
Date: Thu Sep 4 14:13:07 CEST 2008
Subject: [openrisc] Re: OR1K in FPGA
Jeremy Bennett wrote:
> On Tue, 2008-09-02 at 16:41 -0300, Felipe wrote:
>> Hi Jeremy!!!!
>>
>> I am using a XUP Virtex-II Pro of Digilent, it has a usb jtag config
>> connection and a Parallel Cable IV connection.
>>
If you have a Parallel IV cable, use it -- it works with the toolchain
patches at http://www.eecg.utoronto.ca/~jarvin/or32/. I don't know if
these patches are included in the new OR32 toolchain, so your mileage
may vary with that one.
If you grab the drp-0.6.5 tarball, it should include all the toolchain
patches, a collection of makefiles for automating building of the
toolchain, and maybe some documentation and hardware stuff.
It's all a bit out of date now, but I've used it successfully with the
XUPV2P board and a Parallel IV cable.
>> Other problem is the memory interface, in the hardware tutorial of the
>> opencores site, the memory interface is removed, and a small memory is
>> assigned.
>> Now I want to pass the linux image for the openrisc, and I'll need of
>> the memory interface, but in the XUP Virtex-II Pro the memory is
>> SDRAM, and in the or1k the interface is for a SRAM memory........
>> I am using the Xilinx ISE software, and the UCF pins of XUP Virtex-II
>> are different of the Or1k memory interface pins.
It's possible to use the OPB DDR controller that comes with EDK by
writing a small OPB-WB bridge (honest, it's trivial). Xilinx also
provides DDR memory controller IP outside of EDK. There's a couple of
DDR controllers on OpenCores that should also work (wb_ddr and ddr_sdr,
I believe).
> You'll need to write the server side of the OpenRISC 1000 Remote JTAG
> interface to drive the Diligent version. That would be something you
> could contribute back to the OpenCores community. I suggest you use the
> code in Or1ksim (look in the debug sub-directory) as the basis of this.
>
I've looked at the feasibility of using the Digilent USB connection but
I haven't done anything with respect to implementing it yet. To use the
Digilent USB JTAG interface, you have to instantiate the BSCAN_VIRTEX2
primitive instead of connecting the debug module to pins on the FPGA.
Once you've got that aspect taken care of, you can refer to the code at
http://rmdir.de/~michael/xilinx/ to get a sense of how jp2 should be
hacked to communicate over that interface. Also, the scan chain
configuration will be totally different (you'll see the xcv2p30, the
CPLD, and the SystemACE, I think). You'll have to scan to the xcv2p30
then use its interface to access the internal scan chain. There's more
information on using the BSCAN_VIRTEX2 primitive in the Virtex 2 Pro
data book.
Good luck with this. Email this list if you have more XUPV2P-specific
questions and I'll try to help. Cheers,
Mark.
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