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    Navigation: All forums > Openrisc > Message List > Message Post

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    From: Jeremy Bennett<jeremy.bennett@e...>
    Date: Thu Aug 21 09:29:06 CEST 2008
    Subject: [openrisc] Re: OR1K in FPGA
    Top
    On Tue, 8/19/08, Felipe Henes <fhenes@g...> wrote:
    >
    > I am trying to pass a linux image to the OpenRisc running in a Xilinx
    > VirtexII-PRO FPGA, could you help me to do it??????
    >
    > I have the system image running in the simulator and the processor
    > running in the FPGA, but I don't know how to download the system to
    > run in the processor....
    >
    > Can you help me???
    >
    >
    Hi Felipe,

    I've transferred your question to the OpenRISC mailing list, so the
    wider community can participate and benefit.

    There are some short papers on building OpenRISC on FPGA written by
    Patrick Pelgrims, Dries Driessens and Tom Tierens of the De Nayer
    Instituut at the Hogeschool voor WetenSchap & Kunts in Belgium. The
    hardware tutorial can be found on the OR1200 page
    (http://www.opencores.org/projects.cgi/web/or1k/openrisc_1200) and the
    software tutorial on the OpenRISC 1000 toolchain page
    (http://www.opencores.org/projects.cgi/web/or1k/gnu_toolchain_port).

    This is now rather old. The hardware guide will probably help, but it
    sounds like you already have the hardware running. The key is the
    software. This uses GDB to download and run the software on the FPGA.
    However the software paper describes the old GDB 5.0 port for OpenRISC,
    which is nearly 10 years old.

    Since then both OpenRISC and its JTAG interface have evolved. In
    particular there are two flavours of the JTAG interface. The older
    version is included in the ORPSoC RTL tree, the newer version (by Igor
    Bodor) is a separate OpenCores download. The newer version is simpler
    (i.e smaller) and has a slightly different scan chain for CPU control.
    The OpenRISC has also evolved, with different structure to its
    configuration registers.

    I have recently ported GDB 6.8 to OpenRISC 1000, and considerably
    simplified the code. You should use this to interface to your FPGA and
    download software.

    http://www.embecosm.com/download.html

    The key is to understand your JTAG interface. How are you physically
    connecting your workstation? Is it a direct connection, and if so what
    sort of connection? The GDB 6.8 port includes code for direct connection
    via the parallel port to a JP1 header and for remote connection via
    TCP/IP.

    The remote connection is also used for newer hardware connections (e.g.
    USB connections). A small program acts as the server side of the TCP/IP
    connection and drives the actual hardware interface (e.g. USB) - this
    program will be different for each type of hardware interface. ORSoC
    (http://www.orsoc.com/), the owners of www.opencores.org, make and sell
    such a USB JTAG debugger interface).

    If you let us know details of your connection, I'll advise further on
    how to get GDB 6.8 connected, so you can download, run and debug your
    software.

    ATB,


    Jeremy

    --
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