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Message
From: Flavio M. De Paula<depaulfm@c...>
Date: Fri Jul 18 20:35:32 CEST 2008
Subject: [openrisc] What tag version of the RTL should I use that matches
the or1k-sim?
> My feeling is that the core CPU is reasonably accurate. I don't think
> something as big as Linux would work if there were serious errors in the
> instruction modeling. It is an architectural simulator, so don't expect
> perfect cycle counts.
OK! Let's talk from the CPU point-of-view, instead.
1) When passing an image to the or1ksim, does it load each specific
memory section (described in the sim.cfg) based on the address in the
image, or some address translation happens at this point? Let me
illustrate w/ a simple example:
- In sim.cfg, the memory section "FLASH" has addressbase= 0xF0000000;
- If the image has instructions that starts at this address base, will
or1ksim load those instructions into the "FLASH" memory section?
- If I enable log in the "FLASH" memory section by assigning "log =
flash.log", I should see accesses to location above 0xF0000000, shouldn't
I? Unfortunately, I am not. That is what is leading me to believe there is
some address translation happening before the address gets out of the cpu.
2) The IMM is enabled in the or1ksim by default. I assume some
configuration of the page table, and imm registers need to occur before
using it. I believe you do that by default (within your implementation),
in other words, you don't require the image being loaded to configure the
IMM. Is this true?
Thank you,
PS: I could give you the vmlinux so that you'd see what I'm saying. Just
let me know if you need it.
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