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Message
From: Jeremy Bennett<jeremy.bennett@e...>
Date: Thu Jul 17 21:39:38 CEST 2008
Subject: [openrisc] What tag version of the RTL should I use that
matches the or1k-sim?
Hi Flavio,That is a harder question! I don't know, and I suspect there never was a
1:1 correspondence with any particular version of the RTL. Since the
version number is 0.2.0, I would assume there is still a lot of work to
do.
Certainly the match to the wider SoC (like the Traffic COP in
particular) is not complete. For SoC modeling I would only use the
Or1ksim for the CPU core and model anything else I cared about
separately (that was the motivation behind my SystemC application note).
My feeling is that the core CPU is reasonably accurate. I don't think
something as big as Linux would work if there were serious errors in the
instruction modeling. It is an architectural simulator, so don't expect
perfect cycle counts.
Could you explain the problem example in a bit more detail. Everything
you have included is correct. Is it that the program counter does not
subsequently change to 0xf0000118 (after allowing for the delay cycle)?
I seem to recall a problem where Or1ksim gets things wrong if you write
off the end of a memory block (it wraps the address round, rather than
flagging up an error). Do you have memory at 0xf0000118?
The best approach is to post any problems, and we'll see if we can fix
them. And of course the great thing about open source is that you can
always hack the code yourself.
Hope this helps,
Jeremy
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Tel: +44 (1202) 416955
Cell: +44 (7970) 676050
SkypeID: jeremybennett
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-----Original Message-----
From: Flavio M. De Paula <depaulfm@c...>
To: jeremy.bennett@e..., List about OpenRISC project
<openrisc@o...>
Subject: Re: [openrisc] What tag version of the RTL should I use that
matches the or1k-sim?
Date: Thu, 17 Jul 2008 12:11:15 -0700 (PDT)
Hi Jeremy,
Let me try to be more specific on my question. What version of the
openrisc is the ork1sim based on?
A clear difference between version 1/1/04 and or1ksim 0.2.0 is that in the
latter there is a memory controler at address 0x93000000 (I looked in the
sim.cfg file), whereas in the RTL there is no memory controller per say --
meaning, I searched for a memory controller unit, or something that
resembles one, the only thing closer to it is the traffic cop.
The problem I'm having in the RTL is at the 5th instr (see below), when
the cpu is supposed to fetch instruction at address 0xf0000118.
To answer to your e-mail: I have downloaded and installed the new
toolchain. I was able to boot linux 2.6.19. No problem here. But, there
seems to be a clear difference between the actual hardware and the arch
simulator. The aim of this e-mail to make sure I am comparing apples w/
apples.
Thank you for your cooperation. And, yes, once I find bugs I will file
them and suggest fixes.
----- output of or1ksim
r3 =00000001 00000100 l.ori r3,r0,0x1
r3 =00000001 00000104 l.mtspr r0,r3,0x11
r3 =f0000000 00000108 l.movhi r3,0xf000
r3 =f0000118 r3 =f0000118 0000010c l.ori r3,r3,0x118
r3 =f0000118 00000110 l.jr r3
-----------
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