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Message
From: Stephen R Phillips<cyberman_phillips@y...>
Date: Thu Jul 10 03:00:29 CEST 2008
Subject: [openrisc] GPIO interrupt handling? (Opcode Delay slot)
--- On Wed, 7/9/08, Xiang Li <olivercamel@g...> wrote:
> From: Xiang Li <olivercamel@g...>
> Subject: Re: [openrisc] GPIO interrupt handling?
> To: "List about OpenRISC project" <openrisc@o...>
> Date: Wednesday, July 9, 2008, 6:03 AM
> Hi List,
>
> Actually I have the same question for a long time, i.e.
> could someone
> explain a little more about the delay slot to me? Becasue
> there 's too
> few explainations I can find from openrisc documents.
>
> As far as I know, all the the "l.jump"
> instructions will be followed
> one delay slot. The instructions stored in the delay slot
> will be
> performed beform the "l.jump". Do I understand
> correctly? If so, why
> do we have to design such a delay slot? what is it used
> for? why the
> l.jump have to performed after the instructions in the
> delay slot? And
> in the program I 've seen, more then 90%
> "l.jump" is followed by a
> "l.nop", so is the delay slot really necessary,
> why not combine the
> two together?
>
I don't think a delay slot is a FEATURE. My guess is it's there because of the instruction decode pipeline has to be flushed due to a change in instruction flow in which prefetch for opcodes is not already happened. This stall is a waste of execution time so the delay slot is likely to allow someone to make use of this idle processor time instead of letting it go to waste.
> I know this perhaps because of the pipeline of openrisc,
> but again,
> there's no more description for pipeline in the
> document. Thanks a lot
> for help.
If it's not in the documentation, perhaps it should be commented in the source code for the processor or the micro instruction code. Might check in those places. As it SHOULD be documented there (if not ... I'll just sigh and say stuff happens).
Stephen
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