LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Find Resources
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Openrisc > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: rich_daddio at yahoo.com<rich_daddio@y...>
    Date: Wed Jul 9 18:12:59 CEST 2008
    Subject: [openrisc] GPIO interrupt handling?
    Top
    MIPish but might be helpful.
    http://strmnnrmn.blogspot.com/2006/05/branch-delay-instructions.html

    Most MIPS docs contain pretty good explanations of architectural
    reasons for delay slots and how to use and abuse them :).

    The Hennessy books might have some good info too.

    HTH,

    Rich d



    ----- Original Message -----
    From: Xiang Li<olivercamel@g...>
    To:
    Date: Wed Jul 9 12:03:41 CEST 2008
    Subject: [openrisc] GPIO interrupt handling?

    > Hi List,
    >
    > Actually I have the same question for a long time, i.e. could
    > someone
    > explain a little more about the delay slot to me? Becasue there 's
    > too
    > few explainations I can find from openrisc documents.
    > As far as I know, all the the "l.jump" instructions will
    > be followed
    > one delay slot. The instructions stored in the delay slot will be
    > performed beform the "l.jump". Do I understand correctly?
    > If so, why
    > do we have to design such a delay slot? what is it used for? why
    > the
    > l.jump have to performed after the instructions in the delay slot?
    > And
    > in the program I 've seen, more then 90% "l.jump" is
    > followed by a
    > "l.nop", so is the delay slot really necessary, why not
    > combine the
    > two together?
    > I know this perhaps because of the pipeline of openrisc, but again,
    > there's no more description for pipeline in the document. Thanks a
    > lot
    > for help.
    > /Xiang
    > On Tue, Jul 8, 2008 at 9:23 AM, Robert Cragie <rcc at
    > jennic.com> wrote:
    > > As you have put
    > >
    > > l.jalr r2
    > > l.addi r2,r0,0
    > >
    > > then as far as I can see it you have set r2 to 0 in the delay
    > slot, which
    > > will be executed before the jump. Therefore you will be
    > jumping to 0. Try:
    > >
    > > l.jalr r2
    > > l.nop
    > > l.addi r2,r0,0
    > >
    > > Also, maybe think about saving r2 on the stack in the ISR
    > instead of just
    > > clearing it.
    > >
    > > Robert
    > >
    > > silzon at naver.com wrote:
    > >
    > > Hello. I run or1200 RISC on Evaulation board.
    > > I am programming GPIO interrupt system.
    > > It work interrupt service routine, but,
    > > After interrupt service routing is finished, It doen't return
    > back!
    > > my reset.S is..
    > > .org 0x800
    > > _hpint:
    > > l.movhi r2,hi(_isr_gpio)
    > > l.ori r2,r2,lo(_isr_gpio)
    > > l.jalr r2
    > > l.addi r2,r0,0
    > > l.rfe
    > >
    > >
    > > what's wrong??
    > >
    > >
    > > please, help me :)
    > > _______________________________________________
    > > http://www.opencores.org/mailman/listinfo/openrisc
    > >
    > >
    > > --
    > > Robert Cragie, Design Engineer
    > > Direct: +44 (0) 114 281 4512
    > >
    > _______________________________________________________________
    > > Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK
    > > http://www.jennic.com Tel: +44 (0) 114 281 2655 Confidential
    > > > _______________________________________________________________ > > > > _______________________________________________ > > http://www.opencores.org/mailman/listinfo/openrisc > > > >

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.