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From: sergey bryukov<sb.subscribe@g...>
Date: Wed May 21 02:31:13 CEST 2008
Subject: [openrisc] multicore OpenRISC solution
Hello!
Im exploring an opportunity of OpenRISC in multi-core SoC solution where
ever OpenRISC employed as core for HW module.
The idea is extend OpenRISC cores by new instruction set (or add HW) and
interconnect them by direct links like FIFO or Queue (do not utilize the
BUS)...
Is there common way on opencores.org how-to interconnect two OpenRISC cores
by FIFO or other sync?
On example of Tensilica.com RISC cores, specific instructions to move data
from any of 1024 GPIO to internal registers are given.
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