OPENCORES.ORG

Hi !

I ran the Verilog simulation of RT-level OR1200 codes in modelsim,
trying to get some code metrics and i noticed the same problem.
Actually i couldnt managed to have a load hit successfully even when
the whole memory space is set to be cached (`define OR1200_DMMU_CI   
1'b0 - DMMU is not active ). It insists on showing me that every load
is done form cache inhibited area.

Is it a due to the wrong signal change mentioned before? Had it been
fixed?

Thank you in advance.

----- Original Message ----- 
From: Damjan Lampret<damjanl@o...> 
To: 
Date: Thu Jan  5 21:27:53 CET 2006 
Subject: [openrisc] Load hit in OR1200 

> Hi ! 
> 
> Can you send me a test case. Thanks 
> 
> regards 
> Damjan 
> ----- Original Message ----- 
> From: <hhm95 at beethoven.ee.ncku.edu.tw> 
> To: <openrisc at opencores.org> 
> Sent: Thursday, January 05, 2006 6:48 AM 
> Subject: [openrisc] Load hit in OR1200 
> > Hi 
> > 
> > I ran the Verilog simulation of RT-level OR1200 codes. When a 
> load 
> > instruction hits in the data cache, there is a little trouble. 
> The 
> > load is determinsed as a load from cache-inhibited area. (I 
> used VN to 
> > analyze the state transition behavior of the FSM in data 
> cache) It 
> > should be a load hit! 
> > I traced the signals which cause the load from cache-inhibited 
> area 
> > and found that 'dcfsm_first_hit_ack' rises after the FSM 
> enters 
> > '`OR1200_DCFSM_CLOAD' state. The rise of 'dcfsm_first_hit_ack' 
> in 
> > terms de-assert 'dcqmem_cycstb_i'. Thus in next cycle, a load 
> from 
> > inhibited area is found by the codes in the case 
> OR1200_DCFSM_CLOAD 
> > block. How could this happen? Is there any problem in the load 
> hit 
> > behavior? 
> > 
> > Best Regards, 
> > Hung-Min Hsu 
> > EE Dept., NCKU, Taiwan 
> > _______________________________________________ 
> > http://www.opencores.org/mailman/listinfo/openrisc 
> 
> 