|
Message
From: Jose Ignacio Villar<jvillar@g...>
Date: Wed Apr 23 10:54:43 CEST 2008
Subject: [openrisc] Testbench to add two numbers in openrisc OR1200
processor
Hi!
Icarus verilog does a great work simulating openrisc 1200.
If you need more info or help, contact me and i'll send you a pair of
working testbenchs.
Kind regards,
José Ignacio Villar.
On Tue, Apr 22, 2008 at 9:07 AM, ahmadyan <attachment-0001.htm> wrote:
>
> hey.
> for designing testbench program for openrisc you've to cross-compile
> gnu-gcc
> for or1200. then objdump the executable file and put the binary in
> instruction memory.
>
>
> P.S.
> if you want this ASAP you can use this, it's a testbench for Quicksort that
> work on or1200.
> just put it in your Instruction Memory in SOC_top module.
>
> initial
> begin
>
>
> mem[64]=32'h9c21ffd0;
>
> mem[65]=32'hd4011004;
>
> mem[66]=32'h9c410030;
>
> mem[67]=32'hd4014800;
>
> mem[68]=32'h9c600001;
>
> mem[69]=32'hd7e21fd8;
>
> mem[70]=32'h9c600014;
>
> mem[71]=32'hd7e21fdc;
>
> mem[72]=32'h9c60002d;
>
> mem[73]=32'hd7e21fe0;
>
> mem[74]=32'h9c60000f;
>
> mem[75]=32'hd7e21fe4;
>
> mem[76]=32'h9c600005;
>
> mem[77]=32'hd7e21fe8;
>
> mem[78]=32'h9c60001e;
>
> mem[79]=32'hd7e21fec;
>
> mem[80]=32'h9c600019;
>
> mem[81]=32'hd7e21ff0;
>
> mem[82]=32'h9c60000a;
>
> mem[83]=32'hd7e21ff4;
>
> mem[84]=32'h9c600028;
>
> mem[85]=32'hd7e21ff8;
>
> mem[86]=32'h9c600023;
>
> mem[87]=32'hd7e21ffc;
>
> mem[88]=32'h9c62ffd8;
>
> mem[89]=32'h9c800000;
>
> mem[90]=32'h9ca00009;
>
> mem[91]=32'h04000008;
>
> mem[92]=32'h15000000;
>
> mem[93]=32'h9c600000;
>
> mem[94]=32'ha9630000;
>
> mem[95]=32'h85210000;
>
> mem[96]=32'h84410004;
>
> mem[97]=32'h44004800;
>
> mem[98]=32'h9c210030;
>
> mem[99]=32'h9c21ffe8;
>
> mem[100]=32'hd4011004;
>
> mem[101]=32'h9c410018;
>
> mem[102]=32'hd4014800;
>
> mem[103]=32'hd7e21ff8;
>
> mem[104]=32'hd7e227f4;
>
> mem[105]=32'hd7e22ff0;
>
> mem[106]=32'h8462fff4;
>
> mem[107]=32'h8482fff0;
>
> mem[108]=32'he4632000;
>
> mem[109]=32'h10000016;
>
> mem[110]=32'h15000000;
>
> mem[111]=32'h8462fff8;
>
> mem[112]=32'h8482fff4;
>
> mem[113]=32'h84a2fff0;
>
> mem[114]=32'h84c2fff0;
>
> mem[115]=32'h04000014;
>
> mem[116]=32'h15000000;
>
> mem[117]=32'ha86b0000;
>
> mem[118]=32'hd7e21ffc;
>
> mem[119]=32'h8462fffc;
>
> mem[120]=32'h9ca3ffff;
>
> mem[121]=32'h8462fff8;
>
> mem[122]=32'h8482fff4;
>
> mem[123]=32'h07ffffe8;
>
> mem[124]=32'h15000000;
>
> mem[125]=32'h8462fffc;
>
> mem[126]=32'h9c830001;
>
> mem[127]=32'h8462fff8;
>
> mem[128]=32'h84a2fff0;
>
> mem[129]=32'h07ffffe2;
>
> mem[130]=32'h15000000;
>
> mem[131]=32'h85210000;
>
> mem[132]=32'h84410004;
>
> mem[133]=32'h44004800;
>
> mem[134]=32'h9c210018;
>
> mem[135]=32'h9c21ffdc;
>
> mem[136]=32'hd4011004;
>
> mem[137]=32'h9c410024;
>
> mem[138]=32'hd4014800;
>
> mem[139]=32'hd7e21ff0;
>
> mem[140]=32'hd7e227ec;
>
> mem[141]=32'hd7e22fe8;
>
> mem[142]=32'hd7e237e4;
>
> mem[143]=32'h9c600004;
>
> mem[144]=32'h8482ffe4;
>
> mem[145]=32'he0641b06;
>
> mem[146]=32'h8482fff0;
>
> mem[147]=32'he0632000;
>
> mem[148]=32'h84630000;
>
> mem[149]=32'hd7e21ffc;
>
> mem[150]=32'h8462ffe4;
>
> mem[151]=32'h8482ffe8;
>
> mem[152]=32'he4032000;
>
> mem[153]=32'h10000007;
>
> mem[154]=32'h15000000;
>
> mem[155]=32'h8462fff0;
>
> mem[156]=32'h8482ffe4;
>
> mem[157]=32'h84a2ffe8;
>
> mem[158]=32'h0400002f;
>
> mem[159]=32'h15000000;
>
> mem[160]=32'h8462ffec;
>
> mem[161]=32'hd7e21ff8;
>
> mem[162]=32'h8482ffec;
>
> mem[163]=32'hd7e227f4;
>
> mem[164]=32'h8462fff4;
>
> mem[165]=32'h8482ffe8;
>
> mem[166]=32'he4832000;
>
> mem[167]=32'h10000004;
>
> mem[168]=32'h15000000;
>
> mem[169]=32'h00000019;
>
> mem[170]=32'h15000000;
>
> mem[171]=32'h8482fff4;
>
> mem[172]=32'h9c600004;
>
> mem[173]=32'he0641b06;
>
> mem[174]=32'h8482fff0;
>
> mem[175]=32'he0632000;
>
> mem[176]=32'h84830000;
>
> mem[177]=32'h8462fffc;
>
> mem[178]=32'he5441800;
>
> mem[179]=32'h1000000a;
>
> mem[180]=32'h15000000;
>
> mem[181]=32'h8462fff0;
>
> mem[182]=32'h8482fff4;
>
> mem[183]=32'h84a2fff8;
>
> mem[184]=32'h04000015;
>
> mem[185]=32'h15000000;
>
> mem[186]=32'h8462fff8;
>
> mem[187]=32'h9c630001;
>
> mem[188]=32'hd7e21ff8;
>
> mem[189]=32'h8462fff4;
>
> mem[190]=32'h9c630001;
>
> mem[191]=32'hd7e21ff4;
>
> mem[192]=32'h03ffffe4;
>
> mem[193]=32'h15000000;
>
> mem[194]=32'h8462fff0;
>
> mem[195]=32'h8482fff8;
>
> mem[196]=32'h84a2ffe8;
>
> mem[197]=32'h04000008;
>
> mem[198]=32'h15000000;
>
> mem[199]=32'h8462fff8;
>
> mem[200]=32'ha9630000;
>
> mem[201]=32'h85210000;
>
> mem[202]=32'h84410004;
>
> mem[203]=32'h44004800;
>
> mem[204]=32'h9c210024;
>
> mem[205]=32'h9c21fff8;
>
> mem[206]=32'hd4011000;
>
> mem[207]=32'h9c410008;
>
> mem[208]=32'ha8c30000;
>
> mem[209]=32'h9c600004;
>
> mem[210]=32'he0641b06;
>
> mem[211]=32'he0633000;
>
> mem[212]=32'h84630000;
>
> mem[213]=32'hd7e21ffc;
>
> mem[214]=32'h9c600004;
>
> mem[215]=32'he0641b06;
>
> mem[216]=32'he0833000;
>
> mem[217]=32'h9c600004;
>
> mem[218]=32'he0651b06;
>
> mem[219]=32'he0633000;
>
> mem[220]=32'h84630000;
>
> mem[221]=32'hd4041800;
>
> mem[222]=32'h9c600004;
>
> mem[223]=32'he0651b06;
>
> mem[224]=32'he0633000;
>
> mem[225]=32'h8482fffc;
>
> mem[226]=32'hd4032000;
>
> mem[227]=32'h84410000;
>
> mem[228]=32'h44004800;
>
> mem[229]=32'h9c210008;
>
>
>
>
>
> end
>
>
> nehagoel634 wrote:
> >
> > Hi,
> >
> > Can somebody tell me how to write a small test bench to add two
> > numbers in verilog for openrisc OR1200 processor. Also whaich
> > simulation tool should i use to do logic simulation of the architecture.
> >
> > Please reply as early as possible.
> >
> > Thanks
> > _______________________________________________
> > attachment-0001.htm
> >
> >
>
> --
> View this message in context:
> attachment-0001.htm
> Sent from the OpenCores - RISC mailing list archive at Nabble.com.
>
> _______________________________________________
> attachment-0001.htm
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: attachment-0001.htm
|
 |
Browse
