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Message
From: ravotto at tiscali.it<ravotto@t...>
Date: Thu Apr 10 10:25:45 CEST 2008
Subject: [openrisc] or1200 fault simulation
Does anybody is able to make a fault simulation of the entire or1200
processor using synopsys tetramax?
I have synthesized the or1200 using Synopsys design compiler (and a
the script provided with the processor), but when I load the gate
level in Tetramax a strange error occurs when I change the mode to test
Error: Wire gate (997) failed contention ability check for drivers 994
and 996.
Thanks a lot in advance
--
danilo
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