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Message
From: Andreas Ehliar<ehliar@i...>
Date: Tue Mar 25 12:48:58 CET 2008
Subject: [openrisc] or1200 data cache
On Wed, Mar 12, 2008 at 04:41:59PM +0100, liuzg305@1... wrote:
> 1.Does or1200 cache all memory access including registers in the
> wishbone slave module when enable the data cache?
I'm not sure what you mean by this question.
> 2.When I enable the or1200 data cache when power up, do I need to
> disable first when want to read the data from uart?
You can decide which regions to cache by changing some parameters in
cpu_defines.v, look around for "cache inhibit".
>
> 3.I can run the or1k linux2.4 when I disable the data cache.But when I
> enable the data cache,the or1k linux2.4 can not boot up
> successfully.What is the matter?
There are still some cache related bugs in the bugtracker for OpenRisc
on OpenCores. Perhaps you can take a look there to see if they might
be relevant for you.
/Andreas
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