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From: yueng<penguin00@m...>
Date: Thu Feb 21 04:18:01 CET 2008
Subject: [openrisc] does or1ksim support cache?

i install the or1ksim0.2.0rc2

change the sim.cfg :
read mem delay 10
write mem delay 10
no data/inst cache
run a jpegdecode use 3000M cycle,171M instruction.

then i change the sim.cfg
read mem delay 10
write mem delay 10
has data cache , hitdelay 1, miss delay 2
has inst cache , hitdelay 1, miss delay 2.
run the same program,the result is exactly the same 3000M cycle,171M
instruction.

I think if use cache the result should use fewer cycles.

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