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Message
From: yueng<penguin00@m...>
Date: Wed Feb 20 06:09:31 CET 2008
Subject: [openrisc] or1ksim 's question
by the way, where is the executed.log? i didn't find the file at cur dir or in the or1ksim install dir.
Dimitri?s Orfanos wrote: > > There are many answers for these questions. > 1)If you load the linux kernel on or1ksim and on the linux kernel you > run the program then of course you have more > instructions because the simulator runs and the linux kernel. > 2)The openrisc compiler produces code with many NOPs in the brand delay > slots. A better compiler (I haven't try to use the optimization switches > to say the truth , I mean to use the switch -o1 ,-o2 ,etc) could put in > the delay slots more useful code not NOPs. > 3)Does the simulator stops automatically the simulation or you have to > press Ctrl-C? The "exit" function that the compiler uses by default puts > the processor (here the simulator) to infinite loop(by executing NOPs) > after the normal execution of the program. So if you want to stop the > program you press Ctrl-C ,but you are not faster than the computer so > many NOPs came again in your code. > You can check the code that was executed by seeing the file > "executed.log" that is produced from the simulator if you set the > exec_log (or exe_log , I don't remember actually) from the sim.cfg to 1. > That's all I have to say. Hope this helps. > > yueng wrote: >> I change the sim.cfg , mem read and write both delay 1. >> i run jpeg decode in the or1ksim >> the result is >> 310,200,242 cycles, 171,816,396 instructions >> compare with arm7 it use only 56,000,000 cycle, and 40,000,000 >> instructions >> >> i remember that i read or1ksim is about 90% cycle accurate somewhere, >> same jpeg decode C code ,why or1ksim use so many instructions? and so >> many >> cycles. >> >> >> thank you >> > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > >
-- View this message in context: http://www.nabble.com/or1ksim-%27s-question-tp15540185p15582533.html Sent from the OpenCores - RISC mailing list archive at Nabble.com.
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