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Message
From: Hemant Mallapur<hemant@s...>
Date: Thu Feb 14 07:11:36 CET 2008
Subject: [openrisc] OR1200 IC integration queries
Hi,We're planning to use OR1200 in our SOC and had few queries: 1. We want to use the CPU as follows:
(a) without any I-cache and D-cache
(b) without any I-MMU or D-MMU
(c) with dedicated program and data memories
I know we can achieve (a) by using the NO_IC and NO_DC defines and
(b) by using NO_IMMU and NO_DMMU defines. For (c) I'm having a difficulty
- I see there is a qmem instantiated which seems to be non-Harvard style
where same memory is accessed for both Instructions & Data with some
arbitration. Does it mean that I have to modify the qmem code if I want (c)?
Or is there a different
2. I see (from simulations) that reset vector of OR1200 by default is 0x100.
I was wondering why this peculiar address was chosen? Wouldn't a 0 have
sufficed for ease of decoding or is there a good reason to retain this? Is
there a way to change the boot address?
3. We were thinking of an SOC with its BootRom sitting on the Instruction
wishbone interface - is there a better place for this (Qmem maybe?)
4. We have installed the toolchain and seem to be able to compile an assembly testcase
(basic.s) using or32-uclinux-gcc to a binary. I'm not sure how I can use this in a verilog
simulation. Is the binary in coff format? How do I read this into a verilog testbench
memory array (bootrom).
5. Also how do I use the OR simulator output to compare with RTL output and check
that my RTL is up and running? Is there a good doc for me to read up on this?
6. I haven't found any IC Integrator's manual (the Xilinx/Altera tutorials are too
specific) - there is only a programmer's manual. With so many users I'd
have imagined there'd be good links for this by now....
Hemant
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