|
Message
From: ankurrawat0612 at gmail.com<ankurrawat0612@g...>
Date: Thu Jan 10 10:49:37 CET 2008
Subject: [openrisc] help me in runniing or1200 from verilog based test bench
hi all
I am trying to make verilog based test bench for the or1200
which is present in location or1k/orp/orp_soc/rtl/verilog/or1200/
I am giving input(1.addi) to the wishbone interface(which is in read
mode ) ,through or1200_top, keeping all the debug unit inputs as 0(zero).
but in response the or1200_top signs, iwb_cyc_o and iwb_stb_o are
not turning high .
when i am debugging inside i am finding qmem unit whose working is
not clear to me.
are there any other parametrs which are to be set.
please help me in these aspects
ankur
|
 |
Browse
