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Message
From: Matjaz Breskvar<matjazb@b...>
Date: Fri Dec 7 13:02:10 CET 2007
Subject: [openrisc] Openrisc/ DDR2 SDRAM
* Mark (jarvin@e...) wrote:
> Matjaz Breskvar wrote:
> >* fpga_group@y... (fpga_group@y...) wrote:
> >>Can i find anywhere an open IP for sdram ddr2 controller? or
> >>I there any another realizable way to do this?
> >
> You can probably adapt whatever Xilinx provides with the board or
> CoreGen or EDK. I've used the OPB DDR controller from EDK attached
> directly to the WB bus on a XUPV2P board -- OPB and WB are similar
> enough that this works.
>
> There's a DDR controller on OpenCores called ddr_sdr that you also might
> be able to adapt. I don't think DDR and DDR2 are so vastly different
> that this would be implausible.
>
> >I do not think there is a an open IP of good configurable ddr2 sdram
> >controller. You will also need to worry about the physical layer which
> >needs
> >to be taylored to your exact process/technology (or FPGA vendor)
> >
> >Beyond Semiconductor has an affordable multiport DDR2 SDRAM controller
> >available from:
> >
> >http://www.beyondsemi.com/page/products/interface_cores/beyond_ddr_sdram_memory_controller
> >
> Could you be more specific regarding affordability: how much does this
> cost? Also, is 3500 slices small, typical, or large? How large is the
> smallest supported configuration?
for pricing one should contact Beyond Semi.
3500 slices is typical size. the exact number will vary depending on desired
data width, frequency and how many ports one would want.
If just the physical layer + minimal control is desired then Xilinx solution
is the easiest way out. If you want technology independant core with high
efficiency in terms of bandwidths for unpredictable data access patterns
then Beyond DDR2 SDRAM controller is a better option.
r,
p.
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