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From: Andreas Ehliar<ehliar@i...>
Date: Thu Dec 6 16:39:32 CET 2007
Subject: [openrisc] Openrisc/ DDR2 SDRAM
On Wed, Dec 05, 2007 at 07:22:58PM +0100, fpga_group@y... wrote:
> hello,
>
> I am using the openrisc project for the implemenation on a FPGA
> board.That is spartan board (extreDSP with Spratan DSP 1800a)
> containing flash memory and 128 MB DDR2 SDRAM memory. In order to
> implement this, i have to write new RAM Controller istead of urs
> (sram_top). am i right?
>
> Can i find anywhere an open IP for sdram ddr2 controller? or
> I there any another realizable way to do this?

If you just want to get something up and running quickly on your
spartan board you could look at Xilinx' Memory Interface Generator
(MIG) which is freely available (as in beer) if you register with
Xilinx. You will still need to write a wishbone wrapper for it but it
will be substantially easier than developing your own DDR2 SDRAM
controller.

/Andreas