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    Navigation: All forums > Openrisc > Message List > Message Post

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    From: Matjaz Breskvar<matjazb@b...>
    Date: Thu Dec 6 11:41:59 CET 2007
    Subject: [openrisc] Openrisc/ DDR2 SDRAM
    Top
    * fpga_group@y... (fpga_group@y...) wrote:
    > hello,
    >
    > I am using the openrisc project for the implemenation on a FPGA
    > board.That is spartan board (extreDSP with Spratan DSP 1800a)
    > containing flash memory and 128 MB DDR2 SDRAM memory. In order to
    > implement this, i have to write new RAM Controller istead of urs
    > (sram_top). am i right?
    >
    > Can i find anywhere an open IP for sdram ddr2 controller? or
    > I there any another realizable way to do this?

    I do not think there is a an open IP of good configurable ddr2 sdram
    controller. You will also need to worry about the physical layer which needs
    to be taylored to your exact process/technology (or FPGA vendor)

    Beyond Semiconductor has an affordable multiport DDR2 SDRAM controller available from:

    http://www.beyondsemi.com/page/products/interface_cores/beyond_ddr_sdram_memory_controller

    regards,
    m.

    ReferenceAuthor
    [openrisc] Openrisc/ DDR2 SDRAMFpga_group

    Follow upAuthor
    [openrisc] Openrisc/ DDR2 SDRAMMark

     
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