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From: fpga_group at yahoo.de<fpga_group@y...>
Date: Wed Dec 5 19:22:58 CET 2007
Subject: [openrisc] Openrisc/ DDR2 SDRAM
hello,

I am using the openrisc project for the implemenation on a FPGA
board.That is spartan board (extreDSP with Spratan DSP 1800a)
containing flash memory and 128 MB DDR2 SDRAM memory. In order to
implement this, i have to write new RAM Controller istead of urs
(sram_top). am i right?

Can i find anywhere an open IP for sdram ddr2 controller? or
I there any another realizable way to do this?


I hope u can give me any hints or directions..

thank you,

best regards

Follow up	Author
[openrisc] Openrisc/ DDR2 SDRAM	Matjaz Breskvar