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From: ShinJea Tahk<shinje2k@g...>
Date: Tue Oct 25 11:09:48 CEST 2005
Subject: [openrisc] [gcc porting] redundant code sequence
I am trying to make my own or1k simulator and instruction test vectors. All
the basic instructions are okay. So I tried to run the c-level test vectors
like or1k/orp/orp_soc/sw tests. And I used the additional gcc torture test
vector in or1k/gcc-3.2.3/gcc/testsuite/gcc.c-torture/execute. My simulator
got fail for some vectors in gcc.c-torture directory. I checked the error
and I found the redundant code sequence like this.

% or32-uclinux-objdump -D gcc.c-torture/execute/921019-1.or32

opencore
040001a0 <_main>:
40001a0: 9c 21 ff e8 l.addi r1,r1,0xffffffe8
40001a4: d4 01 10 04 l.sw 0x4(r1),r2
40001a8: 9c 41 00 18 l.addi r2,r1,0x18
40001ac: d4 01 48 00 l.sw 0x0(r1),r9
40001b0: 18 60 00 00 l.movhi r3,0x0
40001b4: a8 63 20 00 l.ori r3,r3,0x2000
40001b8: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3
40001bc: 84 62 ff f8 l.lwz r3,0xfffffff8(r2)
40001c0: 84 63 00 00 l.lwz r3,0x0(r3)
40001c4: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3
40001c8: 84 62 ff f4 l.lwz r3,0xfffffff4(r2)
40001cc: 90 63 00 00 l.lbs r3,0x0(r3)

- Ignored:
40001d0: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3
40001d4: 84 62 ff f0 l.lwz r3,0xfffffff0(r2)
40001d8: bc 03 00 58 l.sfeqi r3,0x58
40001dc: 10 00 00 04 l.bf <attachment.html> 40001ec <_main+0x4c>
40001e0: 15 00 00 00 l.nop 0x0
40001e4: 04 00 00 50 l.jal 4000324 <_abort>
40001e8: 15 00 00 00 l.nop 0x0
40001ec: 85 62 ff fc l.lwz r11,0xfffffffc(r2)
40001f0: 85 21 00 00 l.lwz r9,0x0(r1)
40001f4: 84 41 00 04 l.lwz r2,0x4(r1)
40001f8: 44 00 48 00 l.jr r9
40001fc: 9c 21 00 18 l.addi r1,r1,0x18


When you look at 40001b8 address, you can find store & load at the same
address and register.


40001b8: d7 e2 1f fc l.sw 0xfffffffc(r2),r3
40001bc: 84 62 ff fc l.lwz r3,0xfffffffc(r2)
40001c0: 84 63 00 00 l.lwz r3,0x0(r3)


So I check the mips-rtems-gcc
mips
00400100 <main>:
400100: 27bdffe8 addiu sp,sp,-24
400104: afbf0014 sw ra,20(sp)
400108: afbe0010 sw s8,16(sp)
40010c: 03a0f021 move s8,sp
400110: 8f828010 lw v0,-32752(gp)
400114: 00000000 nop
400118: 80430000 lb v1,0(v0)
40011c: 24020058 li v0,88
400120: 10620003 beq v1,v0,400130 <main+0x30>
400124: 00000000 nop
400128: 0c100010 jal 400040 <abort>
40012c: 00000000 nop
400130: 03c0e821 move sp,s8
400134: 8fbf0014 lw ra,20(sp)
400138: 8fbe0010 lw s8,16(sp)
40013c: 03e00008 jr ra
400140: 27bd0018 addiu sp,sp,24

mips looks okay for me. It has reasonable code generation and size.
Even if it's simple test case, there is some code size difference.
17(mips)/24(openrisc)
I like to know which gcc source code should I look at.

And my second issue is uninitialized date read in

gcc.c-torture/execute/20000113-1.c

mips code

0: 27bdffd8 addiu sp,sp,-40
4: afbf0024 sw ra,36(sp)
8: afbe0020 sw s8,32(sp)
c: 03a0f021 move s8,sp
10: afc40028 sw a0,40(s8)
14: afc5002c sw a1,44(s8)
18: afc60030 sw a2,48(s8)
1c: 8fc20028 lw v0,40(s8)
20: 00000000 nop
24: 000227c0 sll a0,v0,0x1f
28: 3c027fff lui v0,0x7fff
2c: 3442ffff ori v0,v0,0xffff
30: 00621824 and v1,v1,v0
34: 00641825 or v1,v1,a0
38: 8fc2002c lw v0,44(s8)
3c: 00000000 nop
40: 30420003 andi v0,v0,0x3
44: 00022740 sll a0,v0,0x1d


openrisc code 40001a0: 9c 21 ff 50 l.addi r1,r1,0xffffff50 40001a4: d4 01 10 04 l.sw 0x4(r1),r2 40001a8: 9c 41 00 b0 l.addi r2,r1,0xb0 40001ac: d4 01 48 00 l.sw 0x0(r1),r9 40001b0: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 40001b4: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4 40001b8: d7 e2 2f f4 l.sw 0xfffffff4(r2),r5 40001bc: 84 62 ff fc l.lwz r3,0xfffffffc(r2) 40001c0: b8 63 00 1f l.slli r3,r3,0x1f 40001c4: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 40001c8: 18 60 7f ff l.movhi r3,0x7fff 40001cc: a8 63 ff ff l.ori r3,r3,0xffff 40001d0: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) 40001d4: e0 64 18 03 l.and r3,r4,r3 openrisc try to read at 40001d0: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) 40001d4: e0 64 18 03 l.and r3,r4,r3 And r4 register used for next "and" instruction. In mips code, it looks there is initialized data read like this... 14: afc5002c sw a1,44(s8) .... 38: 8fc2002c lw v0,44(s8) 3c: 00000000 nop 40: 30420003 andi v0,v0,0x3 I am not sure what I made a mistake. please help me. Regards ShinJea -------------- next part -------------- An HTML attachment was scrubbed... URL: openrisc/attachments/20051025/ec11e1ecattachment.html

Follow up	Author
[openrisc] [gcc porting] redundant code sequence	Johan Rydberg