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From: Andreas Ehliar<ehliar@i...>
Date: Fri Oct 7 18:51:50 CEST 2005
Subject: [openrisc] Instruction cache related bug
Hi,
I discovered another cache related bug, this time in the instruction
cache. In certain cases it is possible for a cacheline to be filled
incorrectly:

| AAAA | BBBB | CCCC | DDDD | <-- correct cacheline
| AAAA | AAAA | CCCC | DDDD | <-- buggy cacheline

I have created a screendump of modelsim where this behaviour is
shown at the following URL:
http://www.da.isy.liu.se/~ehliar/opencores/waveform.png

If you look at /cachebug_top/cpu/iwb_adr_o in the picture you can see
that the address is not changed after the first ACK. I have also
included some signals from the iwb_biu unit where I think the bug is
located. The problem seems to be that the biu_ack_o either happens too
late in case of a repeated access or that the iwb_stb_o/iwb_adr_o
signals are asserted one clock cycle too early. If this is true the
wb_biu should also be checked for this kind of bug.


I have included the testbench that I used in order to create the
behaviour described above:
http://www.da.isy.liu.se/~ehliar/opencores/ifetchbug.tar.gz


/Andreas