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Message
From: Balint Cristian<cristian.balint@o...>
Date: Wed Aug 31 09:35:58 CEST 2005
Subject: [openrisc] ORP_SOC Test bench CLK period
----- Original Message -----
From: "Kory Schoenfliess" <kmschoen@n...>
To: "List about OpenRISC project" <openrisc@o...>
Sent: Wednesday, August 31, 2005 3:05 AM
Subject: [openrisc] ORP_SOC Test bench CLK period
> Hello,
>
> Is there any way of running the ORP_SOC faster than 25MHz (40 ns clock)?
> Whenever I change BENCH_CLK_HALFPERIOD to something lower than 20 (hence
> the 40ns clock), I get unknown values (exceptions) in executed.log and the
> regression fail. I suppose this has something to do with the SRAM and
> FLash models and the or1200 running too fast to get the proper inputs.
> Thanks.
Yes.
Spartan 3S1000 at 50Mhz :)
But its somehow unstable because reach the constrain limit, somewhere at
40Mhz is safe and stable
on a 3S1000-4.
Probaly in Vitex4 is acheiveable more speed.
>
> Kory.
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc
>
>
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