Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: Kory Schoenfliess<kmschoen@n...>
Date: Tue Aug 23 23:51:51 CEST 2005
Subject: [openrisc] Concerning ORP_SOC...
Hello,

After performing an analysis of the ORP_SOC architecture, specifically
the HDL hierachy of 'xsv_fpga_top.v' and below, I have found that the
VGA CRT controller (ssvga_top.v) requires the use of Xilnix block ram
primitives. Has anyone implemented generically for arbitrary synthesis?

Thank you,
Kory Schoenfliess

Follow up	Author
[openrisc] Concerning ORP_SOC...	Damjan Lampret