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From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Tue Jul 5 16:53:26 CEST 2005
Subject: [openrisc] Help with debug interface

> I'm trying to use the jtag debug interface and TAP > controller in a homebrew or1k based SOC but I need > some help with a few questions. I apologise if these > are answered in the mailing list archive but search > doesn't seem to work on it at the moment - You can use google to search the archives (though, I don't know if your questions have been answered before). > Which jtag proxy program should be used with the debug > interface, the jp1 or jp2? I vaguely remember reading > that the protocol changed to jp2 when the interface > and TAP controller were separated. jp1 is used with the older version of the debug interface (the one used in orp_soc/) and jp2 is the newer one (the current release of the jtag tap/debug interface, used in rc203soc/). > If I want to run the jtag proxy and connect to an RTL > sim, what testbench interface do I need? I see that > the orp_soc tree has files called dbg_comm.v and > dbg_comm2.v which seem to have code that looks at > gdb_in.txt and gdb_out.txt but will this work with the > up-to-date debug interface? dbg_comm.v is the one you need. dbg_comm.v just proxies events to and from the outside world (ie. the CLK, TDI, TDO and TMS lines) to/from the tap, so it's not tied to any specific version of the debug interface. If you want to use vpi to proxy the signals you have to apply the attached patch to dbg_comm.v. > Is there any information about using the jtag proxy > with an RTL sim? Only what's in jtag/README. nog. -------------- next part -------------- --- /hd0/or1k/or1k/orp/orp_soc/bench/verilog/dbg_comm.v 2002-03-28 20:59:54.000000000 +0100 +++ orp_soc/bench/verilog/dbg_comm.v 2004-11-27 18:22:25.000000000 +0100 @@ -65,6 +65,9 @@ // // +// Define this if you want to use the VPI to do the communications +//`define DBG_IF_COMM_VPI + `ifdef DBG_IF_COMM `include "timescale.v" @@ -78,6 +81,8 @@ //`define GDB_IN "../src/gdb_in.dat" //`define GDB_OUT "../src/gdb_out.dat" +`define JP_SOCK "/tmp/jp-vpi" + module dbg_comm(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO); parameter Tp = 1; @@ -115,6 +120,9 @@ wb_rst_i = 1; #500; wb_rst_i = 0; +`ifdef DBG_IF_COMM_VPI + $jp_init(`JP_SOCK); +`endif #2000; StartTesting = 1; @@ -129,6 +137,9 @@ while(1) begin #1; +`ifdef DBG_IF_COMM_VPI + $jp_in(memory); +`else $readmemh(`GDB_OUT, memory); //#1000; if(!(memory[0] & 5'b10000)) @@ -137,6 +148,7 @@ $fwrite(handle1, "%h", 5'b10000 | memory[0]); // To ack to jp1 that we read dgb_out.dat $fclose(handle1); end +`endif end end @@ -149,6 +161,10 @@ in_word_r<=#Tp 5'b0; else in_word_r<=#Tp in_word[3:0]; +`ifdef DBG_IF_COMM_VPI + memory[0] <=#Tp memory[0] & 4'b1111; + clk_count= 6'b000000; +`endif end @@ -156,9 +172,13 @@ always @ (posedge P_TCK or alternator) begin +`ifdef DBG_IF_COMM_VPI + $jp_out(P_TDO); +`else handle2 = $fopen(`GDB_IN); - $fdisplay(handle2, "%b", P_TDO); // Vriting output data to file (TDO) + $fdisplay(handle2, "%b", P_TDO); // Writing output data to file (TDO) $fclose(handle2); +`endif end @@ -169,10 +189,28 @@ +`ifdef DBG_IF_COMM_VPI +reg [5:0] clk_count; +always @ (posedge Mclk) +begin + if(!(clk_count & 6'b100000)) + clk_count[5:0]=clk_count[5:0] + 1; +end + +always @ (posedge clk_count[5]) +begin + $jp_wait_time(); +end +`endif + + // Generating master clock (RISC clock) 10 MHz initial begin Mclk<=#Tp 0; +`ifdef DBG_IF_COMM_VPI + clk_count[5:0]<=#Tp 0; +`endif #1 forever #`RISC_CLOCK Mclk<=~Mclk; end

Reference Author

[openrisc] Help with debug interface Simon Jones