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Message
From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Thu Jun 30 17:33:08 CEST 2005
Subject: [openrisc] [or1ksim #87] Fix cache spr handling (resend)
Hi,I sent this patch awile ago and I thought I commited it but apparently I haven't
and I can't find an ack for it, so here it is again.
ChangeLog:
* The effective address as written to the I/DCBPR registers needs to be
translated by the respective mmu.
* Don't treat any values as special in the handling of DCPBR, DCBFR, DCBIR,
ICBPR and ICBIR.
nog
-------------- next part --------------
--- cpu/or1k/sprs.c 2005-05-29 11:54:30.000000000 +0200
+++ ../or1ksim-ac/cpu/or1k/sprs.c 2005-05-30 13:23:04.000000000 +0200
@@ -68,26 +68,21 @@
break;
/* Data cache simulateing stuff */
case SPR_DCBPR:
- if(value) {
- /* FIXME: The arch. manual says "DCBPR is written with the effective
- * address" which suggests it is written with a _virtual_ address,
- * but it seems that the cache sits behind the mmu. How is this
- * address translated then? */
- dc_simulate_read(value, value, 4);
- cpu_state.sprs[SPR_DCBPR] = 0;
- }
+ /* FIXME: This is not correct. The arch. manual states: "Memory accesses
+ * are not recorded (Unlike load or store instructions) and cannot invoke
+ * any exception". If the physical address is invalid a bus error will be
+ * generated. Also if the effective address is not resident in the mmu
+ * the read will happen from address 0, which is naturally not correct. */
+ dc_simulate_read(peek_into_dtlb(value, 0, 1), value, 4);
+ cpu_state.sprs[SPR_DCBPR] = 0;
break;
case SPR_DCBFR:
- if(value != -1) {
- dc_inv(value);
- cpu_state.sprs[SPR_DCBFR] = -1;
- }
+ dc_inv(value);
+ cpu_state.sprs[SPR_DCBFR] = -1;
break;
case SPR_DCBIR:
- if(value != 0) {
- dc_inv(value);
- cpu_state.sprs[SPR_DCBIR] = 0;
- }
+ dc_inv(value);
+ cpu_state.sprs[SPR_DCBIR] = 0;
break;
case SPR_DCBWR:
cpu_state.sprs[SPR_DCBWR] = 0;
@@ -97,20 +92,14 @@
break;
/* Instruction cache simulateing stuff */
case SPR_ICBPR:
- if(value) {
- /* FIXME: The arch. manual says "ICBPR is written with the effective
- * address" which suggests it is written with a _virtual_ address,
- * but it seems that the cache sits behind the mmu. How is this
- * address translated then? */
- ic_simulate_fetch(value, value);
- cpu_state.sprs[SPR_ICBPR] = 0;
- }
+ /* FIXME: The arch manual does not say what happens when an invalid memory
+ * location is specified. I guess the same as for the DCBPR register */
+ ic_simulate_fetch(peek_into_itlb(value, 1), value);
+ cpu_state.sprs[SPR_ICBPR] = 0;
break;
case SPR_ICBIR:
- if(value) {
- ic_inv(value);
- cpu_state.sprs[SPR_ICBIR] = 0;
- }
+ ic_inv(value);
+ cpu_state.sprs[SPR_ICBIR] = 0;
break;
case SPR_ICBLR:
cpu_state.sprs[SPR_ICBLR] = 0;
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