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Message
From: Balaji V. Iyer<bviyer@n...>
Date: Wed Jun 29 18:46:37 CEST 2005
Subject: [openrisc] Does the OR1200 have a 5 stage pipeline?
Hi Andy,
It does have 5 stages. they are: fetch, Decode, Register Read, Execute
and Write Back.
-Balaji V. Iyer.
-----Original Message-----
From: openrisc-bounces@o... [mailto:openrisc-bounces@o...]
On Behalf Of andrewtraill@h...
Sent: Wednesday, June 29, 2005 11:29 AM
To: openrisc@o...
Subject: [openrisc] Does the OR1200 have a 5 stage pipeline?
If so what exactly is each stage (I have an idea what it could be but
I want to verify) and where abouts in the RTL are it/they present? I'm
doing a project where I'll be trying to alter them to run on Razor
based flip-flops to allow in this case overclocking.
Any help is very greatly appreciated.
Thanks,
Andy
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