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Message
From: andrewtraill at hotmail.com<andrewtraill@h...>
Date: Wed Jun 29 17:28:39 CEST 2005
Subject: [openrisc] Does the OR1200 have a 5 stage pipeline?
If so what exactly is each stage (I have an idea what it could be but
I want to verify) and where abouts in the RTL are it/they present? I'm
doing a project where I'll be trying to alter them to run on Razor
based flip-flops to allow in this case overclocking.
Any help is very greatly appreciated.
Thanks,
Andy
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