OPENCORES.ORG

From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Wed Jun 29 16:54:54 CEST 2005
Subject: [openrisc] [or1ksim #112] Remove flag global

Hi,

The flag global mirrored the exact state of SPR_SR_F at all times which has the only advantage of haveing to have lots of extra assignments and checks throught the code. ChangeLog: * Remove the flag global. nog. -------------- next part -------------- diff -upr --unidirectional-new-file ./cpu/or32/execute.c /home/nog/or1ksim-ac/cpu/or32/execute.c --- ./cpu/or32/execute.c 2005-06-28 13:01:05.000000000 +0200 +++ /home/nog/or1ksim-ac/cpu/or32/execute.c 2005-06-12 16:18:55.000000000 +0200 @@ -65,9 +65,6 @@ oraddr_t pcprev = 0; /* Temporary program counter */ oraddr_t pcnext; -/* CCR */ -int flag; - /* Store buffer analysis - stores are accumulated and commited when IO is idle */ static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0; static int sbuf_buf[MAX_SBUF_LEN] = {0}; @@ -576,7 +581,7 @@ void dumpreg() PRINTF("\n"); PRINTF("GPR%.2u: %"PRIxREG" ", i, evalsim_reg(i)); } - PRINTF("flag: %u\n", flag); + PRINTF("flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0); } /* Generated/built in decoding/executing function */ diff -upr --unidirectional-new-file ./cpu/or32/insnset.c /home/nog/or1ksim-ac/cpu/or32/insnset.c --- ./cpu/or32/insnset.c 2005-06-28 13:42:50.000000000 +0200 +++ /home/nog/or1ksim-ac/cpu/or32/insnset.c 2005-06-11 14:04:18.000000000 +0200 @@ -28,8 +28,7 @@ INSTRUCTION (l_add) { SET_PARAM0(temp1); set_ov_flag (temp1); if (ARITH_SET_FLAG) { - flag = temp1 == 0; - if(flag) + if(!temp1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; @@ -55,8 +54,7 @@ INSTRUCTION (l_addc) { SET_PARAM0(temp1); set_ov_flag (temp1); if (ARITH_SET_FLAG) { - flag = temp1 == 0; - if(flag) + if(!temp1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; @@ -149,8 +147,7 @@ INSTRUCTION (l_and) { set_ov_flag (temp1); SET_PARAM0(temp1); if (ARITH_SET_FLAG) { - flag = temp1 == 0; - if(flag) + if(!temp1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; @@ -240,10 +237,10 @@ INSTRUCTION (l_sra) { INSTRUCTION (l_bf) { if (config.bpb.enabled) { int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0; - or1k_mstats.bf[flag][fwd]++; - bpb_update(current->insn_addr, flag); + or1k_mstats.bf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0][fwd]++; + bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0); } - if (flag) { + if(cpu_state.sprs[SPR_SR] & SPR_SR_F) { cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4; btic_update(pcnext); next_delay_insn = 1; @@ -254,10 +251,10 @@ INSTRUCTION (l_bf) { INSTRUCTION (l_bnf) { if (config.bpb.enabled) { int fwd = (PARAM0 >= cpu_state.pc) ? 1 : 0; - or1k_mstats.bnf[!flag][fwd]++; - bpb_update(current->insn_addr, flag == 0); + or1k_mstats.bnf[cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1][fwd]++; + bpb_update(current->insn_addr, cpu_state.sprs[SPR_SR] & SPR_SR_F ? 0 : 1); } - if (flag == 0) { + if (!(cpu_state.sprs[SPR_SR] & SPR_SR_F)) { cpu_state.pc_delay = cpu_state.pc + (orreg_t)PARAM0 * 4; btic_update(pcnext); next_delay_insn = 1; @@ -344,71 +341,61 @@ INSTRUCTION (l_nop) { } } INSTRUCTION (l_sfeq) { - flag = PARAM0 == PARAM1; - if(flag) + if(PARAM0 == PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfne) { - flag = PARAM0 != PARAM1; - if(flag) + if(PARAM0 != PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfgts) { - flag = (orreg_t)PARAM0 > (orreg_t)PARAM1; - if(flag) + if((orreg_t)PARAM0 > (orreg_t)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfges) { - flag = (orreg_t)PARAM0 >= (orreg_t)PARAM1; - if(flag) + if((orreg_t)PARAM0 >= (orreg_t)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sflts) { - flag = (orreg_t)PARAM0 < (orreg_t)PARAM1; - if(flag) + if((orreg_t)PARAM0 < (orreg_t)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfles) { - flag = (orreg_t)PARAM0 <= (orreg_t)PARAM1; - if(flag) + if((orreg_t)PARAM0 <= (orreg_t)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfgtu) { - flag = PARAM0 > PARAM1; - if(flag) + if(PARAM0 > PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfgeu) { - flag = PARAM0 >= PARAM1; - if(flag) + if(PARAM0 >= PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfltu) { - flag = PARAM0 < PARAM1; - if(flag) + if(PARAM0 < PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (l_sfleu) { - flag = PARAM0 <= PARAM1; - if(flag) + if(PARAM0 <= PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; @@ -537,7 +524,7 @@ INSTRUCTION (l_macrc) { cpu_state.sprs[SPR_MACHI] = 0; } INSTRUCTION (l_cmov) { - SET_PARAM0(flag ? PARAM1 : PARAM2); + SET_PARAM0(cpu_state.sprs[SPR_SR] & SPR_SR_F ? PARAM1 : PARAM2); } INSTRUCTION (l_ff1) { SET_PARAM0(ffs(PARAM1)); @@ -567,43 +554,37 @@ INSTRUCTION (lf_rem_s) { SET_PARAM0(temp - (uint32_t)temp); } INSTRUCTION (lf_sfeq_s) { - flag = (float)PARAM0 == (float)PARAM1; - if(flag) + if((float)PARAM0 == (float)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (lf_sfge_s) { - flag = (float)PARAM0 >= (float)PARAM1; - if(flag) + if((float)PARAM0 >= (float)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (lf_sfgt_s) { - flag = (float)PARAM0 > (float)PARAM1; - if(flag) + if((float)PARAM0 > (float)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (lf_sfle_s) { - flag = (float)PARAM0 <= (float)PARAM1; - if(flag) + if((float)PARAM0 <= (float)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (lf_sflt_s) { - flag = (float)PARAM0 < (float)PARAM1; - if(flag) + if((float)PARAM0 < (float)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; } INSTRUCTION (lf_sfne_s) { - flag = (float)PARAM0 != (float)PARAM1; - if(flag) + if((float)PARAM0 != (float)PARAM1) cpu_state.sprs[SPR_SR] |= SPR_SR_F; else cpu_state.sprs[SPR_SR] &= ~SPR_SR_F; --- cpu/or1k/sprs.c 2005-06-28 13:50:53.000000000 +0200 +++ ../or1ksim-split2/cpu/or1k/sprs.c 2005-06-28 15:30:14.000000000 +0200 @@ -116,9 +116,6 @@ mtspr(uint16_t regno, const uorreg_t val cpu_state.sprs[SPR_ICBLR] = 0; break; case SPR_SR: - /* Set internal flag also */ - if(value & SPR_SR_F) flag = 1; - else flag = 0; cpu_state.sprs[regno] |= SPR_SR_FO; #if DYNAMIC_EXECUTION if((value & SPR_SR_IME) && !(prev_val & SPR_SR_IME)) {