OPENCORES.ORG

From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Wed Jun 29 16:53:28 CEST 2005
Subject: [openrisc] [or1ksim #107] Remove useless calls to m{f,t}spr

Hi,

There has been a nice amount of traffic on openrisc in the last days, may aswell add my own :) ChangeLog: * Remove m{f,t}spr calls where we can access the spr directly. nog. -------------- next part -------------- diff -upr --unidirectional-new-file ./cpu/or1k/except.c /home/nog/or1ksim-split2/cpu/or1k/except.c --- ./cpu/or1k/except.c 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/cpu/or1k/except.c 2005-06-28 13:33:15.000000000 +0200 @@ -139,7 +139,7 @@ void except_handle(oraddr_t except, orad /* In immu_translate except_handle is called with except_handle(..., virtaddr) */ /* Add the immu miss delay to the cycle counter */ if(!immu_ex_from_insn) { - mtspr(SPR_EPCR_BASE, get_pc() - (cpu_state.delay_insn ? 4 : 0)); + cpu_state.sprs[SPR_EPCR_BASE] = get_pc() - (cpu_state.delay_insn ? 4 : 0); } else /* This exception came from an l.mtspr instruction in which case the pc * points to the l.mtspr instruction when in acutal fact, it is the next @@ -147,7 +147,7 @@ void except_handle(oraddr_t except, orad * cpu_state.pc + 4 because in the event that the l.mtspr instruction is * in the delay slot of a page local jump the fault must happen on the * instruction that was jumped to. This is handled in recheck_immu. */ - mtspr(SPR_EPCR_BASE, ea); + cpu_state.sprs[SPR_EPCR_BASE] = ea; run_sched_out_of_line(immu_ex_from_insn); /* Save the registers that are in the temporaries */ if(!cpu_state.ts_current) @@ -177,17 +177,17 @@ void except_handle(oraddr_t except, orad upd_reg_from_t(cpu_state.pc, 0); } #endif - mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0)); + cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0); break; /* EPCR is loaded with address of next not-yet-executed instruction */ case EXCEPT_SYSCALL: - mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0)); + cpu_state.sprs[SPR_EPCR_BASE] = (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0); break; /* These exceptions happen AFTER (or before) an instruction has been * simulated, therefore the pc already points to the *next* instruction */ case EXCEPT_TICK: case EXCEPT_INT: - mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0)); + cpu_state.sprs[SPR_EPCR_BASE] = cpu_state.pc - (cpu_state.delay_insn ? 4 : 0); #if !(DYNAMIC_EXECUTION) /* If we don't update the pc now, then it will only happen *after* the next * instruction (There would be serious problems if the next instruction just diff -upr --unidirectional-new-file ./cpu/or1k/sprs.c /home/nog/or1ksim-split2/cpu/or1k/sprs.c --- ./cpu/or1k/sprs.c 2005-05-29 11:54:30.000000000 +0200 +++ /home/nog/or1ksim-split2/cpu/or1k/sprs.c 2005-06-28 13:34:33.000000000 +0200 @@ -50,9 +50,9 @@ int audio_cnt = 0; static FILE *fo = 0; /* Set a specific SPR with a value. */ void -mtspr(uint16_t regno, const sprword value) +mtspr(uint16_t regno, const uorreg_t value) { - sprword prev_val; + uorreg_t prev_val; regno %= MAX_SPRS; prev_val = cpu_state.sprs[regno]; @@ -214,16 +214,48 @@ mtspr(uint16_t regno, const sprword valu } } +/* Get a specific SPR. */ +uorreg_t mfspr(const uint16_t regno) +{ + extern oraddr_t pcprev; + + switch (regno) { + case SPR_NPC: + return cpu_state.pc; + case SPR_PPC: + return pcprev; + case SPR_TTCR: + return spr_read_ttcr(); + default: + /* Links to GPRS */ + if(regno >= 0x0400 && regno < 0x0420) + return cpu_state.reg[regno - 0x0400]; + else if (regno < MAX_SPRS) + return cpu_state.sprs[regno]; + } + if (config.sim.verbose) + PRINTF ("WARNING: read out of SPR range %08X\n", regno); + return 0; +} + /* Show status of important SPRs. */ -void sprs_status() +void sprs_status(void) { - PRINTF("VR : 0x%.8lx UPR : 0x%.8lx\n", mfspr(SPR_VR), mfspr(SPR_UPR)); - PRINTF("SR : 0x%.8lx\n", mfspr(SPR_SR)); - PRINTF("MACLO: 0x%.8lx MACHI: 0x%.8lx\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI)); - PRINTF("EPCR0: 0x%.8lx EPCR1: 0x%.8lx\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1)); - PRINTF("EEAR0: 0x%.8lx EEAR1: 0x%.8lx\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1)); - PRINTF("ESR0 : 0x%.8lx ESR1 : 0x%.8lx\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1)); - PRINTF("TTMR : 0x%.8lx TTCR : 0x%.8lx\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR)); - PRINTF("PICMR: 0x%.8lx PICSR: 0x%.8lx\n", mfspr(SPR_PICMR), mfspr(SPR_PICSR)); - PRINTF("PPC: 0x%.8lx NPC : 0x%.8lx\n", mfspr(SPR_PPC), mfspr(SPR_NPC)); + PRINTF("VR : 0x%"PRIxREG" UPR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_VR], + cpu_state.sprs[SPR_UPR]); + PRINTF("SR : 0x%"PRIxREG"\n", cpu_state.sprs[SPR_SR]); + PRINTF("MACLO: 0x%"PRIxREG" MACHI: 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_MACLO], cpu_state.sprs[SPR_MACHI]); + PRINTF("EPCR0: 0x%"PRIxADDR" EPCR1: 0x%"PRIxADDR"\n", + cpu_state.sprs[SPR_EPCR_BASE], cpu_state.sprs[SPR_EPCR_BASE+1]); + PRINTF("EEAR0: 0x%"PRIxADDR" EEAR1: 0x%"PRIxADDR"\n", + cpu_state.sprs[SPR_EEAR_BASE], cpu_state.sprs[SPR_EEAR_BASE+1]); + PRINTF("ESR0 : 0x%"PRIxREG" ESR1 : 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_ESR_BASE], cpu_state.sprs[SPR_ESR_BASE+1]); + PRINTF("TTMR : 0x%"PRIxREG" TTCR : 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_TTMR], cpu_state.sprs[SPR_TTCR]); + PRINTF("PICMR: 0x%"PRIxREG" PICSR: 0x%"PRIxREG"\n", + cpu_state.sprs[SPR_PICMR], cpu_state.sprs[SPR_PICSR]); + PRINTF("PPC: 0x%"PRIxADDR" NPC : 0x%"PRIxADDR"\n", + cpu_state.sprs[SPR_PPC], cpu_state.sprs[SPR_NPC]); } diff -upr --unidirectional-new-file ./cpu/or1k/sprs.h /home/nog/or1ksim-split2/cpu/or1k/sprs.h --- ./cpu/or1k/sprs.h 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/cpu/or1k/sprs.h 2005-06-28 13:34:33.000000000 +0200 @@ -17,55 +17,37 @@ You should have received a copy of the G along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include "spr_defs.h" - -typedef unsigned long sprword; - /* Prototypes */ -inline void mtspr(uint16_t regno, const sprword value); -static inline sprword mfspr_(const uint16_t regno); -extern sprword sprs[MAX_SPRS]; -#define mfspr(regno) mfspr_(regno) - -static inline void setsprbit(const int regno, const int bitnum, const unsigned long bitvalue); -static inline int getsprbit(const int regno, const int bitnum); -void sprs_status(); - -#include "sim-config.h" -#include "tick.h" - -/* Ugly, but fast */ -/* Get a specific SPR. */ -static inline sprword -mfspr_(const uint16_t regno) +void mtspr(uint16_t regno, const uorreg_t value); +uorreg_t mfspr(const uint16_t regno); +void sprs_status(void); + +/* Set specific SPR bit(s) identified by mask. */ +static inline void +setsprbits(const int regno, const unsigned long mask, const unsigned long value) { - extern oraddr_t pcprev; - - switch (regno) { - case SPR_NPC: - return cpu_state.pc; - case SPR_PPC: - return pcprev; - case SPR_TTCR: - return spr_read_ttcr(); - default: - /* Links to GPRS */ - if(regno >= 0x0400 && regno < 0x0420) - return cpu_state.reg[regno - 0x0400]; - else if (regno < MAX_SPRS) - return cpu_state.sprs[regno]; - } - if (config.sim.verbose) - PRINTF ("WARNING: read out of SPR range %08X\n", regno); - return 0; + uorreg_t regvalue = cpu_state.sprs[regno]; + uorreg_t shifted = 0x0; + int m, v = 0; + + /* m counts bits in valuemask */ + /* v counts bits in value */ + for (m = 0; m < 32; m++) + if ((mask >> m) & 0x1) { + shifted |= ((value >> v) & 0x1) << m; + v++; + } + + /* PRINTF("oldvalue %x setsprbits(%x, %x, %x) shifted %x", regvalue, regno, mask, value, shifted); */ + cpu_state.sprs[regno] = (regvalue & ~mask) | shifted; } /* Get specific SPR bit(s) identified by mask. */ static inline unsigned long getsprbits(const int regno, const unsigned long mask) { - sprword regvalue = cpu_state.sprs[regno]; - sprword shifted = 0x0; + uorreg_t regvalue = cpu_state.sprs[regno]; + uorreg_t shifted = 0x0; int m, v = 0; /* m counts bits in valuemask */ diff -upr --unidirectional-new-file ./cpu/or32/dyn_rec_stubs.c /home/nog/or1ksim-split2/cpu/or32/dyn_rec_stubs.c --- ./cpu/or32/dyn_rec_stubs.c 2005-05-29 11:54:30.000000000 +0200 +++ /home/nog/or1ksim-split2/cpu/or32/dyn_rec_stubs.c 2005-06-28 12:35:06.000000000 +0200 @@ -254,6 +254,11 @@ const char *except_name(oraddr_t except) return NULL; } +uorreg_t mfspr(const uint16_t regno) +{ + return 0; +} + static struct dev_memarea dummy_area = { ops: { delayr: 1 }, }; diff -upr --unidirectional-new-file ./cpu/or32/execute.c /home/nog/or1ksim-split2/cpu/or32/execute.c --- ./cpu/or32/execute.c 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/cpu/or32/execute.c 2005-06-28 13:01:05.000000000 +0200 @@ -472,10 +472,14 @@ void dump_exe_log (void) cpu_state.reg[i]); } fprintf (runtime.sim.fexe_log, "\n"); - fprintf (runtime.sim.fexe_log, "SR : %.8lx ", mfspr(SPR_SR)); - fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx ", mfspr(SPR_EPCR_BASE)); - fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx ", mfspr(SPR_EEAR_BASE)); - fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE)); + fprintf (runtime.sim.fexe_log, "SR : %.8"PRIx32" ", + cpu_state.sprs[SPR_SR]); + fprintf (runtime.sim.fexe_log, "EPCR0: %"PRIxADDR" ", + cpu_state.sprs[SPR_EPCR_BASE]); + fprintf (runtime.sim.fexe_log, "EEAR0: %"PRIxADDR" ", + cpu_state.sprs[SPR_EEAR_BASE]); + fprintf (runtime.sim.fexe_log, "ESR0 : %.8"PRIx32"\n", + cpu_state.sprs[SPR_ESR_BASE]); break; case EXE_LOG_SIMPLE: case EXE_LOG_SOFTWARE: @@ -596,11 +600,11 @@ static inline void decode_execute_wrappe /* Check for range exception */ if((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) && (cpu_state.sprs[SPR_SR] & SPR_SR_OV)) - except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE)); + except_handle (EXCEPT_RANGE, cpu_state.sprs[SPR_EEAR_BASE]); #endif if(breakpoint) - except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE)); + except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]); } /* Reset the CPU */ @@ -684,7 +688,7 @@ inline int cpu_clock () } if(breakpoint) { - except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE)); + except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]); update_pc(); except_pending = 0; return 0; diff -upr --unidirectional-new-file ./cpu/or32/insnset.c /home/nog/or1ksim-split2/cpu/or32/insnset.c --- ./cpu/or32/insnset.c 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/cpu/or32/insnset.c 2005-06-28 13:42:50.000000000 +0200 @@ -299,8 +299,8 @@ INSTRUCTION (l_jr) { cpu_state.pc_delay); } INSTRUCTION (l_rfe) { - pcnext = mfspr(SPR_EPCR_BASE); - mtspr(SPR_SR, mfspr(SPR_ESR_BASE)); + pcnext = cpu_state.sprs[SPR_EPCR_BASE]; + mtspr(SPR_SR, cpu_state.sprs[SPR_ESR_BASE]); } INSTRUCTION (l_nop) { oraddr_t stackaddr; @@ -451,7 +451,7 @@ INSTRUCTION (l_mtspr) { fprintf(runtime.sim.fspr_log, "Write to SPR : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value); } - if (mfspr(SPR_SR) & SPR_SR_SM) + if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) mtspr(regno, value); else { PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n"); @@ -466,7 +466,7 @@ INSTRUCTION (l_mfspr) { fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value); } - if (mfspr(SPR_SR) & SPR_SR_SM) + if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) SET_PARAM0(value); else { SET_PARAM0(0); @@ -475,19 +475,19 @@ INSTRUCTION (l_mfspr) { } } INSTRUCTION (l_sys) { - except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE)); + except_handle(EXCEPT_SYSCALL, cpu_state.sprs[SPR_EEAR_BASE]); } INSTRUCTION (l_trap) { /* TODO: some SR related code here! */ - except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE)); + except_handle(EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]); } INSTRUCTION (l_mac) { - sprword lo, hi; + uorreg_t lo, hi; LONGEST l; orreg_t x, y; - lo = mfspr (SPR_MACLO); - hi = mfspr (SPR_MACHI); + lo = cpu_state.sprs[SPR_MACLO]; + hi = cpu_state.sprs[SPR_MACHI]; x = PARAM0; y = PARAM1; PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y); @@ -497,17 +497,17 @@ INSTRUCTION (l_mac) { /* This implementation is very fast - it needs only one cycle for mac. */ lo = ((ULONGEST)l) & 0xFFFFFFFF; hi = ((LONGEST)l) >> 32; - mtspr (SPR_MACLO, lo); - mtspr (SPR_MACHI, hi); + cpu_state.sprs[SPR_MACLO] = lo; + cpu_state.sprs[SPR_MACHI] = hi; PRINTF ("(%08lx,%08lx)\n", hi, lo); } INSTRUCTION (l_msb) { - sprword lo, hi; + uorreg_t lo, hi; LONGEST l; orreg_t x, y; - lo = mfspr (SPR_MACLO); - hi = mfspr (SPR_MACHI); + lo = cpu_state.sprs[SPR_MACLO]; + hi = cpu_state.sprs[SPR_MACHI]; x = PARAM0; y = PARAM1; @@ -519,22 +519,22 @@ INSTRUCTION (l_msb) { /* This implementation is very fast - it needs only one cycle for msb. */ lo = ((ULONGEST)l) & 0xFFFFFFFF; hi = ((LONGEST)l) >> 32; - mtspr (SPR_MACLO, lo); - mtspr (SPR_MACHI, hi); + cpu_state.sprs[SPR_MACLO] = lo; + cpu_state.sprs[SPR_MACHI] = hi; PRINTF ("(%08lx,%08lx)\n", hi, lo); } INSTRUCTION (l_macrc) { - sprword lo, hi; + uorreg_t lo, hi; LONGEST l; /* No need for synchronization here -- all MAC instructions are 1 cycle long. */ - lo = mfspr (SPR_MACLO); - hi = mfspr (SPR_MACHI); + lo = cpu_state.sprs[SPR_MACLO]; + hi = cpu_state.sprs[SPR_MACHI]; l = (ULONGEST) lo | ((LONGEST)hi << 32); l >>= 28; //PRINTF ("<%08x>\n", (unsigned long)l); SET_PARAM0((orreg_t)l); - mtspr (SPR_MACLO, 0); - mtspr (SPR_MACHI, 0); + cpu_state.sprs[SPR_MACLO] = 0; + cpu_state.sprs[SPR_MACHI] = 0; } INSTRUCTION (l_cmov) { SET_PARAM0(flag ? PARAM1 : PARAM2); diff -upr --unidirectional-new-file ./debug/debug_unit.c /home/nog/or1ksim-split2/debug/debug_unit.c --- ./debug/debug_unit.c 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/debug/debug_unit.c 2005-06-28 13:01:05.000000000 +0200 @@ -98,7 +98,7 @@ int CheckDebugUnit(DebugUnitAction actio return 1; /* is any watchpoint enabled to generate a break or count? If not, ignore */ - if(mfspr(SPR_DMR2) & (SPR_DMR2_WGB | SPR_DMR2_AWTC)) + if(cpu_state.sprs[SPR_DMR2] & (SPR_DMR2_WGB | SPR_DMR2_AWTC)) return calculate_watchpoints(action, udata); return 0; @@ -118,7 +118,7 @@ static int calculate_watchpoints(DebugUn /* Calculate first 8 matchpoints, result is put into DCR_hit */ if (i < 8) { - unsigned long dcr = mfspr(SPR_DCR(i)); + unsigned long dcr = cpu_state.sprs[SPR_DCR(i)]; unsigned long dcr_ct = dcr & SPR_DCR_CT; /* the CT field alone */ /* Is this matchpoint a propos for the current action? */ if ( ((dcr & SPR_DCR_DP) && dcr_ct) && /* DVR/DCP pair present */ @@ -132,7 +132,7 @@ static int calculate_watchpoints(DebugUn ((action==DebugStoreData) && ((dcr_ct == SPR_DCR_CT_SD) || (dcr_ct == SPR_DCR_CT_LSD)))) ) { unsigned long op1 = udata; - unsigned long op2 = mfspr (SPR_DVR(i)); + unsigned long op2 = cpu_state.sprs[SPR_DVR(i)]; /* Perform signed comparison? */ if (dcr & SPR_DCR_SC) { long sop1 = op1, sop2 = op2; /* Convert to signed */ @@ -429,8 +429,8 @@ int debug_get_mem(unsigned int address,u int debug_ignore_exception (unsigned long except) { int result = 0; - unsigned long dsr = mfspr (SPR_DSR); - unsigned long drr = mfspr (SPR_DRR); + unsigned long dsr = cpu_state.sprs[SPR_DSR]; + unsigned long drr = cpu_state.sprs[SPR_DRR]; #if DEBUG_JTAG PRINTF ("dsr 0x%08x drr 0x%08x \n", dsr, drr); @@ -457,7 +457,7 @@ int debug_ignore_exception (unsigned lon PRINTF ("dsr 0x%08x drr 0x%08x result %i\n", dsr, drr, result); #endif - mtspr (SPR_DRR, drr); + cpu_state.sprs[SPR_DRR] = drr; set_stall_state (result != 0); return (result != 0); } diff -upr --unidirectional-new-file ./mmu/dmmu.c /home/nog/or1ksim-split2/mmu/dmmu.c --- ./mmu/dmmu.c 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/mmu/dmmu.c 2005-06-28 13:17:43.000000000 +0200 @@ -64,7 +64,7 @@ inline oraddr_t dmmu_simulate_tlb(oraddr /* Scan all ways and try to find a matching way. */ for (i = 0; i < config.dmmu.nways; i++) - if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) && + if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) && (cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V)) way = i; @@ -86,19 +86,19 @@ inline oraddr_t dmmu_simulate_tlb(oraddr cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6; /* Check if page is cache inhibited */ - data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI; + data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI; runtime.sim.mem_cycles += config.dmmu.hitdelay; - ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize; + ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize; /* Test for page fault */ - if (mfspr (SPR_SR) & SPR_SR_SM) { - if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE) - || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE)) + if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) { + if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE) + || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE)) except_handle(EXCEPT_DPF, virtaddr); } else { - if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE) - || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE)) + if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE) + || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE)) except_handle(EXCEPT_DPF, virtaddr); } @@ -177,7 +177,7 @@ oraddr_t peek_into_dtlb(oraddr_t virtadd /* Scan all ways and try to find a matching way. */ for (i = 0; i < config.dmmu.nways; i++) - if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) && + if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) && (cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_V)) way = i; @@ -188,15 +188,15 @@ oraddr_t peek_into_dtlb(oraddr_t virtadd runtime.sim.cycles); /* Test for page fault */ - if (mfspr (SPR_SR) & SPR_SR_SM) { - if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE) - || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE)) + if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) { + if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SWE) + || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_SRE)) /* otherwise exception DPF would be raised */ return(0); } else { - if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE) - || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE)) + if ( write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_UWE) + || !write_access && !(cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_URE)) /* otherwise exception DPF would be raised */ return(0); @@ -204,10 +204,10 @@ oraddr_t peek_into_dtlb(oraddr_t virtadd if (through_dc) { /* Check if page is cache inhibited */ - data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI; + data_ci = (cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] & SPR_DTLBTR_CI) == SPR_DTLBTR_CI; } - ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize; + ppn = cpu_state.sprs[SPR_DTLBTR_BASE(way) + set] / config.dmmu.pagesize; return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize); } else { /* No, we didn't. */ diff -upr --unidirectional-new-file ./mmu/immu.c /home/nog/or1ksim-split2/mmu/immu.c --- ./mmu/immu.c 2005-06-28 12:44:53.000000000 +0200 +++ /home/nog/or1ksim-split2/mmu/immu.c 2005-06-28 13:31:42.000000000 +0200 @@ -64,7 +64,7 @@ static inline oraddr_t immu_simulate_tlb /* Scan all ways and try to find a matching way. */ for (i = 0; i < config.immu.nways; i++) - if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) && + if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] / (config.immu.pagesize * config.immu.nsets)) == vpn) && (cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V)) way = i; @@ -85,20 +85,20 @@ static inline oraddr_t immu_simulate_tlb cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6; /* Check if page is cache inhibited */ - insn_ci = (mfspr(SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_CI) == SPR_ITLBTR_CI; + insn_ci = (cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_CI) == SPR_ITLBTR_CI; runtime.sim.mem_cycles += config.immu.hitdelay; /* Test for page fault */ - if (mfspr (SPR_SR) & SPR_SR_SM) { - if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) + if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) { + if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_SXE)) except_handle(EXCEPT_IPF, virtaddr); } else { - if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) + if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_UXE)) except_handle(EXCEPT_IPF, virtaddr); } - ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize; + ppn = cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] / config.immu.pagesize; return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize); } else { /* No, we didn't. */ @@ -165,7 +165,7 @@ oraddr_t peek_into_itlb(oraddr_t virtadd /* Scan all ways and try to find a matching way. */ for (i = 0; i < config.immu.nways; i++) - if (((mfspr(SPR_ITLBMR_BASE(i) + set) / (config.immu.pagesize * config.immu.nsets)) == vpn) && + if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] / (config.immu.pagesize * config.immu.nsets)) == vpn) && (cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_V)) way = i; @@ -173,19 +173,19 @@ oraddr_t peek_into_itlb(oraddr_t virtadd if (way >= 0) { /* Yes, we did. */ /* Test for page fault */ - if (mfspr (SPR_SR) & SPR_SR_SM) { - if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_SXE)) { + if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) { + if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_SXE)) { /* no luck, giving up */ return(0); } } else { - if (!(mfspr (SPR_ITLBTR_BASE(way) + set) & SPR_ITLBTR_UXE)) { + if (!(cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] & SPR_ITLBTR_UXE)) { /* no luck, giving up */ return(0); } } - ppn = mfspr(SPR_ITLBTR_BASE(way) + set) / config.immu.pagesize; + ppn = cpu_state.sprs[SPR_ITLBTR_BASE(way) + set] / config.immu.pagesize; return (ppn * config.immu.pagesize) + (virtaddr % config.immu.pagesize); } else { diff -upr --unidirectional-new-file ./pm/pm.c /home/nog/or1ksim-split2/pm/pm.c --- ./pm/pm.c 2005-03-31 16:39:44.000000000 +0200 +++ /home/nog/or1ksim-split2/pm/pm.c 2005-06-28 13:30:42.000000000 +0200 @@ -39,14 +39,13 @@ Foundation, Inc., 675 Mass Ave, Cambridg #include "spr_defs.h" #include "execute.h" #include "sprs.h" - -extern int cont_run; +#include "sim-config.h" /* Reset. It initializes PMR register. */ -void pm_reset() +void pm_reset(void) { if (config.sim.verbose) PRINTF("Resetting Power Management.\n"); - mtspr(SPR_PMR, 0); + cpu_state.sprs[SPR_PMR] = 0; } /*-----------------------------------------------------[ PM Configuration ]---*/

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[openrisc] [or1ksim #107] Remove useless calls to m{f,t}spr Matjaz Breskvar