Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: Damjan Lampret<damjanl@o...>
Date: Mon May 30 12:22:52 CEST 2005
Subject: [openrisc] [or1ksim #87] Fix I/DCBPR ea handling
Yes it should mention that exceptions are not invoked, just like with the
DCBPR.

regards,
Damjan

>> The ICBPR is written with the effective address and the corresponding
>> block from memory is prefetched into the instruction cache.
>> Instruction cache block prefetch is used strictly for improving
>> performance."
>>
>> The bit about exceptions is missing from the ICBPR description. Is this
>> intentional or not?
>
> I think this is accidental. Damjan ?
>