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From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Sun May 29 17:49:24 CEST 2005
Subject: [openrisc] [or1ksim #95] PIC fix
Hi,

This fixes an issue with the PIC when an interrupt gets cleared while they are
dissabled. Prior to this patch the interrupt would be delivered a second time
when the interrupts got enabled again.

ChangeLog:
* Don't issue a pending interrupt when it has already been cleared.

nog.
-------------- next part --------------
diff -upr --unidirectional-new-file ./pic/pic.c ../or1ksim-ac/pic/pic.c
--- ./pic/pic.c 2005-04-27 19:39:34.000000000 +0200
+++ ../or1ksim-ac/pic/pic.c 2005-05-22 16:35:00.000000000 +0200
@@ -58,10 +58,12 @@ void pic_reset()
void pic_clock(void *dat)
{
/* Don't do anything if interrupts not currently enabled */
- if(testsprbits (SPR_SR, SPR_SR_IEE))
+ if(testsprbits (SPR_SR, SPR_SR_IEE)) {
+ TRACE("Delivering interrupt on cycle %lli\n", runtime.sim.cycles);
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
- else
- SCHED_ADD(pic_clock, NULL, 1);
+ } else if(testsprbits (SPR_PICSR, (int)dat))
+ /* Reschedule only if the interrupt hasn't been cleared */
+ SCHED_ADD(pic_clock, dat, 1);
}

/* WARNING: Don't eaven try and call this function *during* a simulated
@@ -85,6 +87,6 @@ void report_interrupt(int line)
except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
} else
/* Interrupts not currently enabled, retry next clock cycle */
- SCHED_ADD(pic_clock, NULL, 1);
+ SCHED_ADD(pic_clock, (void *)line, 1);
}
}