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From: György 'nog' Jeney<nog@s...>
Date: Sun May 29 17:51:10 CEST 2005
Subject: [openrisc] [or1ksim #97] Couple of uart test corrections
Hi,

Changelog says it all.

ChangeLog:
* Correct a couple of tests.

nog.
-------------- next part --------------
diff -upr --unidirectional-new-file ./testbench/acv_uart.c ../or1ksim-ac/testbench/acv_uart.c
--- ./testbench/acv_uart.c 2002-09-12 16:44:30.000000000 +0200
+++ ../or1ksim-ac/testbench/acv_uart.c 2005-05-27 12:50:54.000000000 +0200
@@ -512,7 +514,7 @@ void interrupt_test ()
ASSERT(getreg (UART_IIR) == 0xc1); /* nothing should be happening */
setreg (UART_LCR, LCR_DIVL);
setreg (UART_DLH, 12 >> 8); /* Set relatively slow speed, so we can hanlde interrupts properly */
- setreg (UART_DLL, 12 & 0xff);
+ setreg (UART_DLL, 6 & 0xff);
setreg (UART_LCR, 0x03); /* 8N1 @ 6 */

ASSERT (int_cnt == 0); /* We should not have got any interrupts before this test */
@@ -722,6 +724,10 @@ void control_register_test ()
send_char ('!');
recv_char ('!');
MARK ();
+
+ /* Make sure the TX fifo and the TX serial reg. are empty */
+ ASSERT (getreg (UART_LSR) & LSR_TXFE);
+ ASSERT (getreg (UART_LSR) & LSR_TXE);

/* FCR2 - reset tx FIFO */
send_char_no_wait ('1');
@@ -729,7 +735,7 @@ send_char_no_wait ('2');
// send_char ('1');
// send_char ('2');
setreg (UART_FCR, 4); /* Should clear '2' from fifo, but '1' should be sent OK */
- ASSERT (getreg (UART_LSR) == 0x00); /* we should still be sending '1' */
+ ASSERT (getreg (UART_LSR) == 0x20); /* we should still be sending '1' */
NO_ERROR();
send_char ('*');
recv_char ('*');