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Message
From: Matjaz Breskvar<phoenix@o...>
Date: Mon May 30 12:04:31 CEST 2005
Subject: [openrisc] [or1ksim #87] Fix I/DCBPR ea handling
* Gy?rgy 'nog' Jeney (nog@n...) wrote:
> > the DCBPR and ICBPR should have the same description as far as i know. i'm
> > not sure though, what happens if physical address (after translation) is
> > invalid and would trigger a bus exception. (according to arch manual, no
> > exception should be raised, so it's an no-op, nothing gets changed in the
> > cache, ...)
>
> Not really. The arch. manual about DCBPR:
>
> "The data cache block prefetch register is an optional special-purpose register
> accessible with the l.mtspr/l.mfspr instructions in bots user and supervisor
> modes. It is 32 bits wide in 32-bit implementation and 64 bits wide in 64-bit
> implementations. An implementation may choose not to implement this register
> and ignore all writes to this register.
> The DCBPR is written with the effective address and the corresponding
> block from memory is prefetched into the cache. Memory accesses are not
> recorded (unlike load or store instructions) and cannot invode any exception.
> A data cache block prefetch is used strictly for improvint performance"
>
> While it has this to say about the ICBPR:
>
> "The isntruction cache block prefetch register is an optional special-purpose
> register accessible with the l.mtspr/l.mfspr instructions in both user and
> supervisor modes. It is 32 bits wide in 32-bit implementation and 64 bits wide
> in 64-bit implementations. An implementation may choose not to implement this
> register and ignore all writes to this register.
> The ICBPR is written with the effective address and the corresponding
> block from memory is prefetched into the instruction cache.
> Instruction cache block prefetch is used strictly for improving
> performance."
>
> The bit about exceptions is missing from the ICBPR description. Is this
> intentional or not?
I think this is accidental. Damjan ?
> > > Nearly all handling of the cache control registers checks the value being
> > > written in one way or another, but the arch. manual doesn't provide any such
> > > restrictions. Should it?
> >
> > i'm not sure what you're reffering to. can you give an example.
>
> I'm refering to this:
>
> case SPR_DCBPR:
> if(value) {
> ^^^^^^^^^
> and:
>
> case SPR_DCBFR:
> if(value != -1) {
> ^^^^^^^^^^^^^^^
> and other similar stuff with the instruction cache.
This looks to me like sw. hack. No, there are no 'special' values to be
specialy interpreted by cache...
best regards,
p.
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