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Message
From: Matjaz Breskvar<phoenix@o...>
Date: Mon May 23 00:02:21 CEST 2005
Subject: [openrisc] [or1ksim #87] Fix I/DCBPR ea handling
* Gy?rgy 'nog' Jeney (nog@s...) wrote:
> Hi,
>
> As discussed, the effective address as written to the I/DCBPR registers is a
> virtual address and must be translated by the mmus. This patch fixes this. I
> have more questions about the cache control registers. The arch manual has this
> to say about the DCBPR "Memory accesses are not recorded (Unlike load or store
> instructions) and cannot invoke any exception". Which is pretty clear but there
> is no such text for the ICBPR register. I guess it should be the same as for
> the DCBPR.
the DCBPR and ICBPR should have the same description as far as i know. i'm
not sure though, what happens if physical address (after translation) is
invalid and would trigger a bus exception. (according to arch manual, no
exception should be raised, so it's an no-op, nothing gets changed in the
cache, ...)
> Nearly all handling of the cache control registers checks the value being
> written in one way or another, but the arch. manual doesn't provide any such
> restrictions. Should it?
i'm not sure what you're reffering to. can you give an example.
> ChangeLog:
> * The effective address as written to the I/DCBPR registers needs to be
> translated by the respective mmu.
patch is ok (ie improvment).
regards,
p.
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