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Message
From: =?unknown-8bit?Q?Gy=F6rgy?= 'nog' Jeney<nog@s...>
Date: Fri May 20 12:58:51 CEST 2005
Subject: [openrisc] [or1ksim #87] Fix I/DCBPR ea handling
Hi,As discussed, the effective address as written to the I/DCBPR registers is a
virtual address and must be translated by the mmus. This patch fixes this. I
have more questions about the cache control registers. The arch manual has this
to say about the DCBPR "Memory accesses are not recorded (Unlike load or store
instructions) and cannot invoke any exception". Which is pretty clear but there
is no such text for the ICBPR register. I guess it should be the same as for
the DCBPR.
Nearly all handling of the cache control registers checks the value being
written in one way or another, but the arch. manual doesn't provide any such
restrictions. Should it?
ChangeLog:
* The effective address as written to the I/DCBPR registers needs to be
translated by the respective mmu.
nog.
-------------- next part --------------
--- cpu/or1k/sprs.c 2005-05-13 22:05:34.000000000 +0200
+++ ../or1ksim-ac/cpu/or1k/sprs.c 2005-05-20 12:46:19.000000000 +0200
@@ -69,11 +69,12 @@
/* Data cache simulateing stuff */
case SPR_DCBPR:
if(value) {
- /* FIXME: The arch. manual says "DCBPR is written with the effective
- * address" which suggests it is written with a _virtual_ address,
- * but it seems that the cache sits behind the mmu. How is this
- * address translated then? */
- dc_simulate_read(value, value, 4);
+ /* FIXME: This is not correct. The arch. manual states: "Memory accesses
+ * are not recorded (Unlike load or store instructions) and cannot invoke
+ * any exception". If the physical address is invalid a bus error will be
+ * generated. Also if the effective address is not resident in the mmu
+ * the read will happen from address 0, which naturally not correct. */
+ dc_simulate_read(peek_into_dtlb(value, 0, 1), value, 4);
cpu_state.sprs[SPR_DCBPR] = 0;
}
break;
@@ -98,11 +99,9 @@
/* Instruction cache simulateing stuff */
case SPR_ICBPR:
if(value) {
- /* FIXME: The arch. manual says "ICBPR is written with the effective
- * address" which suggests it is written with a _virtual_ address,
- * but it seems that the cache sits behind the mmu. How is this
- * address translated then? */
- ic_simulate_fetch(value, value);
+ /* FIXME: The arch manual does not say what happens when an invalid memory
+ * location is specified. I guess the same as for the DCBPR register */
+ ic_simulate_fetch(peek_into_itlb(value, 1), value);
cpu_state.sprs[SPR_ICBPR] = 0;
}
break;
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