|
Message
From: Damjan Lampret<damjanl@o...>
Date: Sun May 15 13:27:40 CEST 2005
Subject: [openrisc] [or1ksim #85] [RFC] Overhoul memory code
> Another question, what is the `effective address' of the bus error if it
> is
> generated while refilling a cache line but not while getting the data that
> was
> asked for? In the present code it's that of the access that prompted the
> refill
> in the first place. I'm not convinced that this always such a good idea.
> (However, I do realise that this is something that should never happen).
>
>From software (programming model) viewpoint, a cache line is not something
that you see. If there is a error on the bus associated with the effective
address of for example load instruction, then bus error is the same as
effective address of the load instruction (from where you load) and error on
the bus should cause Bus Error Exception (if bus errors are implemented in
that particular cpu implementation). If that particular load instruction
completes OK from programming standpoint, however causes that a subsequent
cache line refill causes an error on the bus, then the CPU will not get a
bus error exception (because load instruction completed OK from the
programming standpoint), however failure of completing cache line refill
should cause invalidation of that particular cache line.
regards
Damjan
|
 |
Browse
